DRS Servo Timer Configuration

Servo:

• MG996R datasheet.
• Requires 50 Hz (20 ms) period and 1-2 ms duty cycle.

Timer 5 clock configuration:

• TIM5_CH1 on PA0.
• Clock source from APB1 @ 64 MHz (latest clock tree config)
• Maximum prescaler of (2^16 - 1) = 65535 brings TIM5 clock rate to 976.577 Hz
• To achieve 50 Hz, need to count up to 50 / 976.577 = 0.0511992 of timer period
• For a 32 bit timer, then max count is 0.0511992 * (2^32 - 1) = 219898889.5
• So the closest counter reset value is 219898889 = 0xD1B6409

Required range:

• Counter period is 20ms
• So 1-2ms is between 5-10% of counter reset period
• 5% of 219898889 is 10994944 = 0xA7C500
• 10% of 219898889 is 21989888 = 0x14F8A00
• So compare match should be between 0xA7C500 and 0x14F8A00 for a 1-2ms pulse