brot ps2, parallel algorithms design pattern

frameworks/boards/brot/board.json

@@ -18,7 +18,8 @@
         {"set"    : "parallel_screen", "define" : "PARALLEL_SCREEN=1"},
         {"set"    : "qpsram", "define" : "QPSRAM=1"},
         {"set"    : "sync_in",  "define" : "SYNC_IN=1"},
-        {"set"    : "sync_out", "define" : "SYNC_OUT=1"}
+        {"set"    : "sync_out", "define" : "SYNC_OUT=1"},
+        {"set"    : "ps2", "define" : "PS2=1"}
       ],
       "builders": [
         {

frameworks/boards/brot/brot.v

@@ -121,6 +121,10 @@ module top(
   output GPIO0,  // TX
   input  GPIO1, // RX
 `endif
+`ifdef PS2
+  input  GPIO2, // clock
+  input  GPIO3, // data
+`endif
 `ifdef PMOD_COM_OUT
   output PMOD_B1,
   output PMOD_B2,
@@ -278,6 +282,10 @@ M_main __main(
   .out_uart_tx(GPIO0),
   .in_uart_rx (GPIO1),
 `endif
+`ifdef PS2
+  .in_ps2_clock(GPIO2),
+  .in_ps2_data(GPIO3),
+`endif
 `ifdef SYNC_IN
   .in_sync(PMOD_A1),
 `endif

frameworks/boards/ulx3s/ulx3s.v

@@ -102,6 +102,10 @@ module top(
   input  clk_25mhz
   );
 
+
+// ------------------- TODO: 'fake' pin declaration in MAIN_GLUE
+wire flash_clk; // ECP5 specific, see https://github.com/mattvenn/basic-ecp5-pcb/issues/3
+
 wire ready = 0;
 reg [15:0] RST_d;
 reg [15:0] RST_q;
@@ -132,16 +136,14 @@ M_main __main(
 );
 
 `ifdef SPIFLASH
-wire __main_flash_clk;   /// TODO
 USRMCLK usrmclk_flash(
-          .USRMCLKI(__main_flash_clk),
+          .USRMCLKI(flash_clk),
           .USRMCLKTS(1'b0));
 `endif
 
-`ifdef QSPIFLASH          /// TODO
-wire __main_flash_clk;
+`ifdef QSPIFLASH
 USRMCLK usrmclk_flash(
-          .USRMCLKI(__main_flash_clk),
+          .USRMCLKI(flash_clk),
           .USRMCLKTS(1'b0));
 `endif
 

tests/parallel1.si

@@ -0,0 +1,38 @@
+
+// design pattern of parallelzing computations with pipeline syntax
+
+// this means you can effectively have multiple algorithms in parallel!
+// (each can run its own while (1) loop for instance)
+
+unit main(output uint8 leds)
+{
+
+  uint32 cycle(0);
+
+  algorithm {
+
+         // we start two 'pipelines' that will run in parallel
+         // they have only two stages, the first does nothing, the second
+         // executes the task (of course the pipelines could be deeper, here
+         // just showing the most direct parallelizatoin of two tasks)
+
+        {  ->  __display("compute core 0");
+
+          uint3 a=0;
+          while (a != 7) { a = a + 1; __display("[0:%d] a = %d",cycle,a); }
+
+        }
+
+        { ->  __display("compute core 1");
+
+          uint3 b=0;
+          while (b != 7) { b = b + 1; __display("[1:%d] b = %d",cycle,b); }
+
+        }
+
+  }
+
+  always_after {
+    cycle = cycle + 1;
+  }
+}

tests/pipeline30.si

@@ -1,5 +1,5 @@
 
-// nested pipelines test
+// goto in pipeline test
 
 algorithm main(output uint8 leds)
 {