ice-v swirl cache, pll fix for icarus, cache fix in 2x domain crossing

sylefeb · Oct 27, 2023 · 8c47f4e · 8c47f4e
1 parent 6227b4c
commit 8c47f4e
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Showing 2 changed files with 28 additions and 12 deletions.
diff --git a/projects/ice-v/SOCs/ice-v-soc-swirl-cache.si b/projects/ice-v/SOCs/ice-v-soc-swirl-cache.si
@@ -45,14 +45,16 @@ unit pll(
   output  uint1 clock1x,
   output  uint1 rst
 ) {
-  uint2 counter(0);
-  uint8 reset_counter(255);
+  uint2       counter(0);
+  uint8       reset_counter(255);
   passthrough _(inv <: clock, outv :> clock2x);
-  always {
-    rst           = (reset_counter != 0);
-    reset_counter = (reset_counter != 0) ? reset_counter-1 : 0;
-    clock1x = counter[0,1]; // x2 slower
-    counter = counter + 1;
+  algorithm <autorun> {
+    while (1) {
+      rst           = (reset_counter != 8d0);
+      reset_counter = (reset_counter != 8d0) ? (reset_counter-1) : 0;
+      clock1x       = counter[0,1]; // x2 slower
+      counter       = counter + 1;
+    }
   }
 }
 $$end
@@ -83,7 +85,7 @@ $include('swirl-cache.si')
 
 unit main( // I guess this is the SOC :-D
   output uint5 leds,
-$$if not VERILATOR then
+$$if not SIMULATION then
   inout   uint1 ram_io0,
   inout   uint1 ram_io1,
   inout   uint1 ram_io2,
@@ -114,7 +116,7 @@ $$else
   uint1 clock1x = uninitialized;
   uint1 clock2x = uninitialized;
   uint1 rst     = uninitialized;
-  pll clkgen<@clock>(
+  pll clkgen<@clock,!reset>(
     clock1x :> clock1x,
     clock2x :> clock2x,
     rst     :> rst
@@ -213,7 +215,7 @@ $$end
   algorithm {
 $$if SIMULATION and not BARE then
     //while (1) { }
-	  while (cycle < 10000) { }
+	  while (cycle < 1000000) { }
     __display("stopping at cycle %d",cycle);
 $$else
     while (1) { }

diff --git a/projects/ice-v/SOCs/swirl-cache.si b/projects/ice-v/SOCs/swirl-cache.si
@@ -102,8 +102,9 @@ $$end
     ram_io0 <:> ram_io0,    ram_io1 <:> ram_io1,
     ram_io2 <:> ram_io2,    ram_io3 <:> ram_io3,
   );
+  uint1 reg_ram_datanext(0);
+  adapt_data_next _<@clock2x>(data_next_2x <: ram.data_next, data_next :> reg_ram_datanext);
   uint8 reg_ram_rdata(0);
-  uint8 reg_ram_datanext(0);
 
   uint1 update_lines_todo(0);
   uint1 update_lines_done(0);
@@ -290,7 +291,6 @@ $$end
     qwen0     = mem0.wenable; qwen1     = mem1.wenable;
     // cross clock domain
     reg_ram_rdata    = ram.rdata;
-    reg_ram_datanext = ram.data_next;
     /*
     __display("[%d] >> cache status out: @%x|@%x q: @%x|@%x miss: %b|%b ln: %x|%x ln@: %x|%x  lnw: %b|%b",
                 cycle,mem0.addr<<2,mem1.addr<<2,
@@ -310,3 +310,17 @@ $$end
 }
 
 // --------------------------------------------------
+// unit to adapt data next signal across clock domain
+// - should run at 2x
+// --------------------------------------------------
+
+unit adapt_data_next(input uint1 data_next_2x, output uint1 data_next)
+{
+  uint2 dnext(0);
+  always {
+    dnext     = data_next_2x ? 2b11 : {1b0,dnext[1,1]};
+    data_next = dnext[0,1];
+  }
+}
+
+// --------------------------------------------------