ice-v swirl, cleanup, comments

sylefeb · Nov 14, 2023 · a707676 · a707676
1 parent b0281e4
commit a707676
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Showing 3 changed files with 18 additions and 3 deletions.
diff --git a/projects/ice-v/CPUs/ice-v-swirl.si b/projects/ice-v/CPUs/ice-v-swirl.si
@@ -97,9 +97,9 @@ $$print("====== ice-v swirl (pipeline, data bypass, rdcycle) ======")
 // - the register written by stage 4 at this cycle            [case b]
 // - none of the above: we have to wait and hold the pipeline [case c]
 //
-// case a) input register value incorrect
+// case a) input register value incorrect due to write at i-1
 //    due to [write at i-1] => mux
-// case b) setup register value incorrect, ALU and store
+// case b) setup register value incorrect due to write at i
 //    due to [write at i  ] => mux
 // case c) instruction in stage 3 /will/ invalidate a setup register
 //    due to [write at i+1] => hold

diff --git a/projects/ice-v/SOCs/ice-v-soc-swirl-cache.si b/projects/ice-v/SOCs/ice-v-soc-swirl-cache.si
@@ -255,7 +255,7 @@ $$end
   algorithm {
 $$if SIMULATION and not BARE then
     //while (1) { }
-	  while (cycle < 4000) { }
+	  while (cycle < 250) { }
     __display("stopping at cycle %d",cycle);
 $$else
     while (1) { }

diff --git a/projects/ice-v/src/test_pip.s b/projects/ice-v/src/test_pip.s
@@ -0,0 +1,15 @@
+.globl _start
+
+_start:
+
+addi t0,zero,0
+
+addi t1,t0,1
+addi t2,t1,1
+addi t3,t2,1
+addi t4,t3,1
+addi t5,t4,1
+addi t6,t5,1
+
+_end:
+jal _end