BRAM simulation matching yosys, minor edits to qpsram, brot

sylefeb · Nov 1, 2023 · de29189 · de29189
1 parent 254de73
commit de29189
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Showing 5 changed files with 39 additions and 8 deletions.
diff --git a/frameworks/boards/brot/board.json b/frameworks/boards/brot/board.json
@@ -15,7 +15,9 @@
         {"set"    : "pmod_com_out", "define" : "PMOD_COM_OUT=1"},
         {"set"    : "pmod_com_in", "define" : "PMOD_COM_IN=1"},
         {"set"    : "parallel_screen", "define" : "PARALLEL_SCREEN=1"},
-        {"set"    : "qpsram", "define" : "QPSRAM=1"}
+        {"set"    : "qpsram", "define" : "QPSRAM=1"},
+        {"set"    : "sync_in",  "define" : "SYNC_IN=1"},
+        {"set"    : "sync_out", "define" : "SYNC_OUT=1"}
       ],
       "builders": [
         {

diff --git a/frameworks/boards/brot/brot.v b/frameworks/boards/brot/brot.v
@@ -138,6 +138,12 @@ module top(
   inout  PMOD_A8,
   inout  PMOD_A9,
   output PMOD_A10,
+`endif
+`ifdef SYNC_IN
+  input PMOD_A1,
+`endif
+`ifdef SYNC_OUT
+  output PMOD_B9,
 `endif
   input  CLK_48
   );
@@ -230,6 +236,12 @@ M_main __main(
   .out_uart_tx(GPIO0),
   .in_uart_rx(GPIO1),
 `endif
+`ifdef SYNC_IN
+  .in_sync(PMOD_A1),
+`endif
+`ifdef SYNC_OUT
+  .out_sync(PMOD_B9),
+`endif
 // -----------------------------------------------------------------------------
 /*
 PMOD com wiring:
@@ -265,5 +277,6 @@ PMOD_A8 is on a global buffer on the 'in fpga' and has to be used for the clock
 `endif
   .in_run(run_main)
 );
+// -----------------------------------------------------------------------------
 
 endmodule
diff --git a/frameworks/boards/icarus/icarus.v b/frameworks/boards/icarus/icarus.v
@@ -25,7 +25,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 (header_2_M)
 
 */
-`define ICARUS 1
+`define ICARUS      1
+`define SIMULATION  1
+
 $$ICARUS      = 1
 $$SIMULATION  = 1
 $$NUM_LEDS    = 8

diff --git a/frameworks/boards/verilator/verilator.v b/frameworks/boards/verilator/verilator.v
@@ -28,6 +28,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 `define VERILATOR         1
 `define COLOR_DEPTH       6
 `define SDRAM_WORD_WIDTH 16
+`define SIMULATION        1
 
 $$VERILATOR   = 1
 $$NUM_LEDS    = 8

diff --git a/frameworks/templates/bram_generic.v.in b/frameworks/templates/bram_generic.v.in
@@ -6,12 +6,25 @@ input                  [%ADDR_WIDTH%-1:0]    in_addr,
 output reg %DATA_TYPE% [%DATA_WIDTH%-1:0]    out_rdata,
 input                                        clock
 );
-(* no_rw_check *) reg %DATA_TYPE% [%DATA_WIDTH%-1:0] buffer[%DATA_SIZE%-1:0];
-always @(posedge clock) begin
-  if (in_wenable) begin
-    buffer[in_addr] <= in_wdata;
+  (* no_rw_check *) reg %DATA_TYPE% [%DATA_WIDTH%-1:0] buffer[%DATA_SIZE%-1:0];
+`ifdef SIMULATION
+  // in simulation we use a different code that matches yosys output with
+  // no_rw_check enabled (which we use to preserve compact LUT designs)
+  always @(posedge clock) begin
+    if (in_wenable) begin
+      buffer[in_addr] <= in_wdata;
+      out_rdata       <= in_wdata;
+    end else begin
+      out_rdata       <= buffer[in_addr];
+    end
   end
-  out_rdata <= buffer[in_addr];
-end
+`else
+  always @(posedge clock) begin
+    if (in_wenable) begin
+      buffer[in_addr] <= in_wdata;
+    end
+    out_rdata <= buffer[in_addr];
+  end
+`endif
 %INITIAL%
 endmodule