Merge pull request #99 from vacantron/dev

Fix incorrect encoding of second phase IR
sysprog21 · Dec 23, 2023 · 43dda26 · 43dda26
2 parents c86e0fd + beca98a
commit 43dda26
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/src/reg-alloc.c b/src/reg-alloc.c
@@ -405,7 +405,7 @@ void reg_alloc()
                     break;
                 case OP_assign:
                     src0 = prepare_operand(bb, insn->rs1, -1);
-                    dest = prepare_dest(bb, insn->rd, ir->src0, -1);
+                    dest = prepare_dest(bb, insn->rd, src0, -1);
                     ir = bb_add_ph2_ir(bb, insn->opcode);
                     ir->src0 = src0;
                     ir->dest = dest;
@@ -534,8 +534,8 @@ void reg_alloc()
                 case OP_log_and:
                 case OP_log_or:
                     src0 = prepare_operand(bb, insn->rs1, -1);
-                    src1 = prepare_operand(bb, insn->rs2, ir->src0);
-                    dest = prepare_dest(bb, insn->rd, ir->src0, ir->src1);
+                    src1 = prepare_operand(bb, insn->rs2, src0);
+                    dest = prepare_dest(bb, insn->rd, src0, src1);
                     ir = bb_add_ph2_ir(bb, insn->opcode);
                     ir->src0 = src0;
                     ir->src1 = src1;
@@ -545,7 +545,7 @@ void reg_alloc()
                 case OP_bit_not:
                 case OP_log_not:
                     src0 = prepare_operand(bb, insn->rs1, -1);
-                    dest = prepare_dest(bb, insn->rd, ir->src0, -1);
+                    dest = prepare_dest(bb, insn->rd, src0, -1);
                     ir = bb_add_ph2_ir(bb, insn->opcode);
                     ir->src0 = src0;
                     ir->dest = dest;