Computer Assignments (CAs) for Digital Logic Design

This repository contains the Computer Assignments (CAs) for the Digital Logic Design course at the University of Tehran . These assignments focus on various topics in digital system design, including Verilog, SystemVerilog coding, RTL design, combinational and sequential logic, and hardware synthesis.

Computer Assignments (CAs)

This section contains the Computer Assignments (CAs) for the Digital Logic Design course at the University of Tehran . The assignments focus on different aspects of digital system design, ranging from Verilog gate-level modeling to complex RTL and synthesis in SystemVerilog.

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CA 1-2: Basic Switch and Gate Structures in Verilog

• Overview : The first two assignments focus on designing a One's Counter using basic gate and switch structures in Verilog. The circuit calculates the number of 1’s on the data inputs using CMOS gate structures. The assignment also covers cascaded structures for larger circuits.
• Key Concepts : CMOS gate design, Verilog gate primitives, switch-level and gate-level modeling, and timing analysis.

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CA 3: Combinational RTL Design, Simulation, and Synthesis

• Overview : In this assignment, students design a 16-bit Arithmetic Logic Unit (ALU) capable of performing several operations, including addition, bitwise AND/OR, and 2’s complement. The ALU design is described at both the behavioral and structural levels using SystemVerilog. The assignment involves both pre- and post-synthesis simulations.
• Key Concepts : ALU design, RTL description, Yosys synthesis, timing analysis, and gate-level design.

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CA 4: SR-Latch and Delay Analysis

• Overview : The task involves generating an SR-latch with active-low inputs and analyzing the delays involved in using multiple transistors. Students design circuits at the transistor level, focusing on accurate delay calculations and Verilog modeling.
• Key Concepts : SR-latch design, Verilog/SystemVerilog, delay analysis, and transistor-level modeling.

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CA 5: Latches, Flip-Flops, and Serial Transmitter Design

• Overview : In this assignment, students design a serial transmitter circuit that detects a start-sequence and transmits bits based on the input received. The assignment uses sequential logic, latches, and flip-flops to implement the system and requires state machine design for control flow.
• Key Concepts : Sequential logic, state machine design, latches, flip-flops, Verilog/SystemVerilog, and Quartus synthesis.

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CA 6: Accelerator RTL Design for cos(x) Calculation

• Overview : The final assignment involves designing an accelerator for calculating cos(x) using Taylor series expansion. The design consists of a datapath and control unit implemented in SystemVerilog. Students use Quartus to synthesize and simulate the design, performing both pre- and post-synthesis analysis.
• Key Concepts : RTL design, Taylor series expansion, datapath and controller design, lookup-table ROM, and SystemVerilog modeling.

Homework Assignments

This repository contains the homework assignments for the Digital Logic Design course at the University of Tehran . These assignments cover fundamental and advanced topics in digital logic, circuit design, SystemVerilog programming, and synthesis.

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HW 1: Binary and Boolean Operations

• Objective : Perform binary-to-decimal conversions, understand signed and unsigned binary operations, and design basic logic gates.
• Key Concepts : Binary operations, 2’s complement, signed/unsigned addition, and gate-level Verilog descriptions.

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HW 2-3: CMOS and Karnaugh Maps

• Objective : Implement switch-level CMOS circuits and minimize Boolean functions using Karnaugh Maps (K-Maps).
• Key Concepts : CMOS design, AOI (And-Or-Invert) gates, Boolean minimization using K-Maps, and Verilog simulations for delay analysis.

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HW 4: Minimization and Hazards

• Objective : Minimize logic functions using Boolean algebra and Karnaugh Maps. Identify and eliminate hazards in combinational circuits.
• Key Concepts : Logic minimization using NAND/NOR gates, two-level minimization, and detecting static and dynamic hazards in circuits.

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HW 5-6: Logic Synthesis and RTL Design

• Objective : Synthesize logic circuits and combinational RTL components using SystemVerilog. Understand 2's complement circuits, full-adder designs, and binary decoders.
• Key Concepts : 2's complement circuits, full-adder design, multiplexer-based implementations, and binary decoder synthesis.

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HW 7: Combinational RTL Components

• Objective : Design RTL combinational components, such as BCD to Seven-Segment decoders and priority encoders. Cascade and instantiate components using Verilog.
• Key Concepts : BCD to Seven-Segment decoder, priority encoders, and RTL component design using generate statements.

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HW 8: Programmable Logic Devices (PLDs)

• Objective : Implement logic circuits using Programmable Logic Arrays (PLAs) and design a Seven-Segment Display decoder.
• Key Concepts : PLA design, sum-of-products expressions, and Seven-Segment Display decoders.

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HW 9: Counters and Registers

• Objective : Implement counters and registers using SystemVerilog. Design flip-flop-based circuits and develop synchronous/asynchronous counters.
• Key Concepts : Flip-flops, shift registers, synchronous and asynchronous counters, and timing analysis.

How to Run

1. Clone the repository to your local machine.
2. Open the appropriate assignment folder for each CA.
3. Use a Verilog or SystemVerilog simulator (e.g., ModelSim , Quartus ) to compile and simulate the designs.
4. Follow the instructions provided in each assignment for detailed steps on how to simulate and synthesize the design.

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Deliverables

Each assignment typically requires the following deliverables:

• Hand-drawn circuit diagrams or RTL schematics
• Verilog/SystemVerilog code for the design
• Simulation results and testbenches
• Synthesis reports (Yosys, Quartus) and post-synthesis analysis
• Timing diagrams and gate-level analysis

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License

This project is licensed under the MIT License. For more details, see the LICENSE file.