RgGen has been re-implemented so this repositry is no longer maintained. RgGen is maintained here.
RgGen is a code generator tool for SoC/IP/FPGA/RTL engineers. It will automatically generate source code for control/status registers, e.g. RTL, UVM RAL model, C header file, from its register map document. Also RgGen is customizable so you can build your specific generate tool.
RgGen is written in the Ruby programing language and supports version 2.3 or later. If you don't have above version of Ruby, you need to install the Ruby at first. To install the Ruby, see this page.
To install RgGen and required libraries, use the following command:
$ gem install rggen
RgGen will be installed under your system root.
If you want to install them on other location, you need to specify the install directory and set the GEM_PATH environment variable like below:
$ gem install --install-dir YOUR_INSTALL_DIRECTORY rggen
$ export GEM_PATH=YOUR_INSTALL_DIRECTORY
See this page
After checking out the repo, run bin/setup to install dependencies. Then, run rake spec to run the tests.
To install this gem onto your local machine, run bundle exec rake install. To release a new version, update the version number in version.rb, and then run bundle exec rake release, which will create a git tag for the version, push git commits and tags, and push the .gem file to rubygems.org.
If you have any questions, problems, ideas or somethings, you can post them on the following ways:
Bug reports and pull requests are welcome on GitHub at https://github.com/taichi-ishitani/rggen. This project is intended to be a safe, welcoming space for collaboration, and contributors are expected to adhere to the Contributor Covenant code of conduct.
Copyright © 2015-2018 Taichi Ishitani. See LICENSE.txt for further details.