Makefile: Implement plateforms defined in cva6 specification (openhwg…

…roup#769)

* Makefile: Implement the plateforms defined in cva6 specification
target variable can take cv64a6_imacfd_sv39, cv32a6_imac_sv0,
                         cv32a6_imac_sv32, cv32a6_imacf_sv32

Signed-off-by: Jean-Roch Coulon <[email protected]>

* Fix plateform name: from imacfd to imafdc
                    from imacf to imafc

Signed-off-by: Jean-Roch Coulon <[email protected]>

Bender.yml

@@ -202,7 +202,7 @@ sources:
     - corev_apu/src/tech_cells_generic/src/pulp_clock_mux2.sv
     - target: not(cv32a6)
       files:
-      - core/include/cv64a6_imacfd_sv39_config_pkg.sv
+      - core/include/cv64a6_imafdc_sv39_config_pkg.sv
     - target: cv32a6
       files:
       - core/include/cv32a6_imac_sv0_config_pkg.sv

Makefile

@@ -71,13 +71,13 @@ ifdef spike-tandem
     endif
 endif
 
+# target takes one of the following cva6 hardware configuration:
+# cv64a6_imafdc_sv39, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32
+target     ?= cv64a6_imafdc_sv39
+
 # Sources
 # Package files -> compile first
-ifeq ($(findstring 32, $(variant)),32)
-    ariane_pkg := core/include/cv32a6_imac_sv0_config_pkg.sv
-else
-    ariane_pkg := core/include/cv64a6_imacfd_sv39_config_pkg.sv
-endif
+ariane_pkg := core/include/$(target)_config_pkg.sv
 ariane_pkg += core/include/riscv_pkg.sv                              \
               corev_apu/riscv-dbg/src/dm_pkg.sv                      \
               core/include/ariane_pkg.sv                             \
@@ -227,7 +227,7 @@ src :=  $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
         corev_apu/tb/common/SimJTAG.sv
 
 # SV32 MMU for CV32, SV39 MMU for CV64
-ifeq ($(findstring 32, $(variant)),32)
+ifeq ($(findstring 32, $(target)),32)
     src += $(wildcard core/mmu_sv32/*.sv)
 else
     src += $(wildcard core/mmu_sv39/*.sv)

core/Flist.cv32a6_imac_sv32

@@ -0,0 +1,150 @@
+//////////////////////////////////////////////////////////////////////////////
+//
+// Copyright 2021 OpenHW Group
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://solderpad.org/licenses/
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+//
+///////////////////////////////////////////////////////////////////////////////
+//
+// Manifest for the CVA6 CORE RTL model.
+//   - This is a CORE-ONLY manifest.
+//   - Relevent synthesis and simulation scripts/Makefiles must set the shell
+//     ENV variable CVA6_REPO_DIR.
+//
+///////////////////////////////////////////////////////////////////////////////
+
++define+WT_DCACHE
+
++incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/include/
++incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/src/
++incdir+${CVA6_REPO_DIR}/common/local/util/
+
+${CVA6_REPO_DIR}/core/include/cv32a6_imac_sv0_config_pkg.sv
+// Broken (?) dependencies in packages:
+//    - include/ariane_pkg.sv is dependent on src/riscv-dbg/src/dm_pkg.sv
+//      (ariane should not depend on debug-module)
+${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
+// TODO: should not be needed.
+${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv
+${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
+// TODO: ariane_axi_pkg is dependent on this.
+${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
+${CVA6_REPO_DIR}/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
+${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
+
+// Packages
+${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
+${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
+${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
+${CVA6_REPO_DIR}/core/include/axi_intf.sv
+${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
+
+// Common Cells
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/fifo_v3.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/lfsr.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/lzc.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/rr_arb_tree.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/shift_reg.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/unread.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/popcount.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/exp_backoff.sv
+
+// Floating point unit
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_pkg.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_cast_multi.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_classifier.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_divsqrt_multi.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_fma_multi.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_fma.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_noncomp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_block.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_fmt_slice.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_multifmt_slice.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_rounding.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_top.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
+
+// Top-level source files (not necessarily instantiated at the top of the cva6).
+${CVA6_REPO_DIR}/core/ariane.sv
+${CVA6_REPO_DIR}/core/alu.sv
+// Note: depends on fpnew_pkg, above
+${CVA6_REPO_DIR}/core/fpu_wrap.sv
+${CVA6_REPO_DIR}/core/branch_unit.sv
+${CVA6_REPO_DIR}/core/compressed_decoder.sv
+${CVA6_REPO_DIR}/core/controller.sv
+${CVA6_REPO_DIR}/core/csr_buffer.sv
+${CVA6_REPO_DIR}/core/csr_regfile.sv
+${CVA6_REPO_DIR}/core/decoder.sv
+${CVA6_REPO_DIR}/core/ex_stage.sv
+${CVA6_REPO_DIR}/core/instr_realign.sv
+${CVA6_REPO_DIR}/core/id_stage.sv
+${CVA6_REPO_DIR}/core/issue_read_operands.sv
+${CVA6_REPO_DIR}/core/issue_stage.sv
+${CVA6_REPO_DIR}/core/load_unit.sv
+${CVA6_REPO_DIR}/core/load_store_unit.sv
+${CVA6_REPO_DIR}/core/mult.sv
+${CVA6_REPO_DIR}/core/multiplier.sv
+${CVA6_REPO_DIR}/core/serdiv.sv
+${CVA6_REPO_DIR}/core/perf_counters.sv
+${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
+${CVA6_REPO_DIR}/core/re_name.sv
+// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
+${CVA6_REPO_DIR}/core/scoreboard.sv
+${CVA6_REPO_DIR}/core/store_buffer.sv
+${CVA6_REPO_DIR}/core/amo_buffer.sv
+${CVA6_REPO_DIR}/core/store_unit.sv
+${CVA6_REPO_DIR}/core/commit_stage.sv
+${CVA6_REPO_DIR}/core/axi_shim.sv
+
+// What is "frontend"?
+${CVA6_REPO_DIR}/core/frontend/btb.sv
+${CVA6_REPO_DIR}/core/frontend/bht.sv
+${CVA6_REPO_DIR}/core/frontend/ras.sv
+${CVA6_REPO_DIR}/core/frontend/instr_scan.sv
+${CVA6_REPO_DIR}/core/frontend/instr_queue.sv
+${CVA6_REPO_DIR}/core/frontend/frontend.sv
+
+// Cache subsystem
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_ctrl.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_mem.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_missunit.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_wbuffer.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
+
+// Physical Memory Protection
+// NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
+${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
+${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
+
+// Tracer (behavioral code, not RTL)
+${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
+${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
+${CVA6_REPO_DIR}/common/local/util/sram.sv
+
+// MMU Sv32
+${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv
+${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
+${CVA6_REPO_DIR}/core/mmu_sv32/cva6_tlb_sv32.sv
+
+// end of manifest

core/Flist.cv32a6_imafc_sv32

@@ -0,0 +1,150 @@
+//////////////////////////////////////////////////////////////////////////////
+//
+// Copyright 2021 OpenHW Group
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://solderpad.org/licenses/
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+//
+///////////////////////////////////////////////////////////////////////////////
+//
+// Manifest for the CVA6 CORE RTL model.
+//   - This is a CORE-ONLY manifest.
+//   - Relevent synthesis and simulation scripts/Makefiles must set the shell
+//     ENV variable CVA6_REPO_DIR.
+//
+///////////////////////////////////////////////////////////////////////////////
+
++define+WT_DCACHE
+
++incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/include/
++incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/src/
++incdir+${CVA6_REPO_DIR}/common/local/util/
+
+${CVA6_REPO_DIR}/core/include/cv32a6_imac_sv0_config_pkg.sv
+// Broken (?) dependencies in packages:
+//    - include/ariane_pkg.sv is dependent on src/riscv-dbg/src/dm_pkg.sv
+//      (ariane should not depend on debug-module)
+${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
+// TODO: should not be needed.
+${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv
+${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
+// TODO: ariane_axi_pkg is dependent on this.
+${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
+${CVA6_REPO_DIR}/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
+${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
+
+// Packages
+${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
+${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
+${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
+${CVA6_REPO_DIR}/core/include/axi_intf.sv
+${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
+
+// Common Cells
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/fifo_v3.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/lfsr.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/lzc.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/rr_arb_tree.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/shift_reg.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/unread.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/popcount.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/exp_backoff.sv
+
+// Floating point unit
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_pkg.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_cast_multi.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_classifier.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_divsqrt_multi.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_fma_multi.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_fma.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_noncomp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_block.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_fmt_slice.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_multifmt_slice.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_rounding.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_top.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
+
+// Top-level source files (not necessarily instantiated at the top of the cva6).
+${CVA6_REPO_DIR}/core/ariane.sv
+${CVA6_REPO_DIR}/core/alu.sv
+// Note: depends on fpnew_pkg, above
+${CVA6_REPO_DIR}/core/fpu_wrap.sv
+${CVA6_REPO_DIR}/core/branch_unit.sv
+${CVA6_REPO_DIR}/core/compressed_decoder.sv
+${CVA6_REPO_DIR}/core/controller.sv
+${CVA6_REPO_DIR}/core/csr_buffer.sv
+${CVA6_REPO_DIR}/core/csr_regfile.sv
+${CVA6_REPO_DIR}/core/decoder.sv
+${CVA6_REPO_DIR}/core/ex_stage.sv
+${CVA6_REPO_DIR}/core/instr_realign.sv
+${CVA6_REPO_DIR}/core/id_stage.sv
+${CVA6_REPO_DIR}/core/issue_read_operands.sv
+${CVA6_REPO_DIR}/core/issue_stage.sv
+${CVA6_REPO_DIR}/core/load_unit.sv
+${CVA6_REPO_DIR}/core/load_store_unit.sv
+${CVA6_REPO_DIR}/core/mult.sv
+${CVA6_REPO_DIR}/core/multiplier.sv
+${CVA6_REPO_DIR}/core/serdiv.sv
+${CVA6_REPO_DIR}/core/perf_counters.sv
+${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
+${CVA6_REPO_DIR}/core/re_name.sv
+// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
+${CVA6_REPO_DIR}/core/scoreboard.sv
+${CVA6_REPO_DIR}/core/store_buffer.sv
+${CVA6_REPO_DIR}/core/amo_buffer.sv
+${CVA6_REPO_DIR}/core/store_unit.sv
+${CVA6_REPO_DIR}/core/commit_stage.sv
+${CVA6_REPO_DIR}/core/axi_shim.sv
+
+// What is "frontend"?
+${CVA6_REPO_DIR}/core/frontend/btb.sv
+${CVA6_REPO_DIR}/core/frontend/bht.sv
+${CVA6_REPO_DIR}/core/frontend/ras.sv
+${CVA6_REPO_DIR}/core/frontend/instr_scan.sv
+${CVA6_REPO_DIR}/core/frontend/instr_queue.sv
+${CVA6_REPO_DIR}/core/frontend/frontend.sv
+
+// Cache subsystem
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_ctrl.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_mem.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_missunit.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_wbuffer.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
+
+// Physical Memory Protection
+// NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
+${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
+${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
+
+// Tracer (behavioral code, not RTL)
+${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
+${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
+${CVA6_REPO_DIR}/common/local/util/sram.sv
+
+// MMU Sv32
+${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv
+${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
+${CVA6_REPO_DIR}/core/mmu_sv32/cva6_tlb_sv32.sv
+
+// end of manifest

core/Flist.cv64a6_imafdc_sv39

@@ -31,7 +31,7 @@
 +incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/src/
 +incdir+${CVA6_REPO_DIR}/common/local/util/
 
-${CVA6_REPO_DIR}/core/include/cv64a6_imacfd_sv39_config_pkg.sv
+${CVA6_REPO_DIR}/core/include/cv64a6_imafdc_sv39_config_pkg.sv
 // Broken (?) dependencies in packages:
 //    - include/ariane_pkg.sv is dependent on src/riscv-dbg/src/dm_pkg.sv
 //      (ariane should not depend on debug-module)

core/include/cv32a6_imac_sv32_config_pkg.sv

@@ -0,0 +1,15 @@
+// Copyright 2021 Thales DIS design services SAS
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+// You may obtain a copy of the License at https://solderpad.org/licenses/
+//
+// Original Author: Jean-Roch COULON ([email protected])
+
+
+package cva6_config_pkg;
+
+    localparam CVA6ConfigXlen = 32;
+
+endpackage

core/include/cv32a6_imafc_sv32_config_pkg.sv

@@ -0,0 +1,15 @@
+// Copyright 2021 Thales DIS design services SAS
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+// You may obtain a copy of the License at https://solderpad.org/licenses/
+//
+// Original Author: Jean-Roch COULON ([email protected])
+
+
+package cva6_config_pkg;
+
+    localparam CVA6ConfigXlen = 32;
+
+endpackage