Layout of 4bit Ripple Carry Adder formed using CMOS logic in gpdk180nm technology node done in Cadence Virtuoso with no DRC and LVS errors.
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Aug 7, 2024
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cmos-logic
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This repository contains the design, simulation, and performance evaluation of a CMOS NAND Gate using Cadence Virtuoso. The project highlights the design principles and operational characteristics of a fundamental digital logic gate implemented with CMOS technology.
layout cadence-virtuoso cadence nmos vlsi-circuits vlsi-design pmos cmos-circuits cmos-vlsi cmos-logic low-power-vlsi-design
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Jan 6, 2025
Performance Analysis of a 4-bit Ripple Carry Adder (RCA) formed using Static CMOS, Transmission Gate, NMOS Pass Transistor Logic at gpdk 180nm Technology node.
projects schematic vlsi cadence-virtuoso propagation-delay power-analysis 4bits ripple-carry-adder cmos-logic pass-transistor-logic transmission-gate-logic
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Sep 22, 2024
180nm CMOS Design And Implementation of a Seven Segment Display Controller Using a 4-bit Binary Input (The repository with same name is created long ago and a new repository with the same name is created later and the contents in the repository is updated)
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Dec 14, 2024
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