This project will soon be superseded by Tydi-lang2, which uses CHISEL as backend to generate synthesizable FPGA code

Tydi-lang

what is Tydi-lang?

Tydi-lang is designed to be a FPGA accelerator language, integrating Tydi-spec to map complex and dynamiclly sized data structures to hardware streams.

What is the language syntax?

A short cheat sheet is available.

Some "hello world" examples are also available here.

Notice that examples #9~#14 illustrate how to convert SQL queries to Tydilang code. The build results are in the "build" folder. VHDL code are in "4_vhdl/proj".

"12_tpch_sql3" provides a full compile output at here.

How to compile the code?

Compile this Rust binary with cargo.

What does the Tydi-lang complier do?

How Tydi-lang helps accelerator designs?

Related works:

• til-vhdl: a backend to generate VHDL fromm Tydi-IR.

• Fletcher: a tool to generate hardware interface to access Apache Arrow data on memory via PCIE (not yet integrated).