shl and shr

uwplse · May 27, 2024 · 40ec0e5 · 40ec0e5
1 parent b5e3c59
commit 40ec0e5
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Showing 5 changed files with 42 additions and 38 deletions.
diff --git a/bril-rs/src/conversion.rs b/bril-rs/src/conversion.rs
@@ -228,6 +228,8 @@ impl TryFrom<AbstractInstruction> for Instruction {
                     "smax" => ValueOps::Smax,
                     "smin" => ValueOps::Smin,
                     "sub" => ValueOps::Sub,
+                    "shl" => ValueOps::Shl,
+                    "shr" => ValueOps::Shr,
                     #[cfg(feature = "ssa")]
                     "phi" => ValueOps::Phi,
                     #[cfg(feature = "float")]

diff --git a/bril-rs/src/program.rs b/bril-rs/src/program.rs
@@ -427,6 +427,10 @@ pub enum ValueOps {
     Smax,
     /// Signed min
     Smin,
+    /// Shift left
+    Shl,
+    /// Shift right
+    Shr,
     /// <https://capra.cs.cornell.edu/bril/lang/ssa.html#operations>
     #[cfg(feature = "ssa")]
     Phi,
@@ -515,6 +519,8 @@ impl Display for ValueOps {
             Self::Select => write!(f, "select"),
             Self::Smax => write!(f, "smax"),
             Self::Smin => write!(f, "smin"),
+            Self::Shl => write!(f, "shl"),
+            Self::Shr => write!(f, "shr"),
             #[cfg(feature = "ssa")]
             Self::Phi => write!(f, "phi"),
             #[cfg(feature = "float")]

diff --git a/brilift/src/translator.rs b/brilift/src/translator.rs
@@ -374,6 +374,8 @@ impl CompileEnv<'_> {
             bril::ValueOps::Fsub => ir::Opcode::Fsub,
             bril::ValueOps::Fmul => ir::Opcode::Fmul,
             bril::ValueOps::Fdiv => ir::Opcode::Fdiv,
+            bril::ValueOps::Shl => ir::Opcode::Ishl,
+            bril::ValueOps::Shr => ir::Opcode::Ushr,
             _ => panic!("not a translatable opcode: {op}"),
         }
     }
@@ -476,7 +478,9 @@ impl CompileEnv<'_> {
                 | bril::ValueOps::Mul
                 | bril::ValueOps::Div
                 | bril::ValueOps::And
-                | bril::ValueOps::Or => {
+                | bril::ValueOps::Or
+                | bril::ValueOps::Shl
+                | bril::ValueOps::Shr => {
                     self.gen_binary(builder, args, dest, op_type, Self::translate_op(*op));
                 }
                 bril::ValueOps::Select => {

diff --git a/brilirs/src/check.rs b/brilirs/src/check.rs
@@ -95,7 +95,15 @@ fn type_check_instruction<'a>(
       update_env(env, dest, const_type)
     }
     Instruction::Value {
-      op: ValueOps::Add | ValueOps::Sub | ValueOps::Mul | ValueOps::Div,
+      op:
+        ValueOps::Add
+        | ValueOps::Sub
+        | ValueOps::Mul
+        | ValueOps::Div
+        | ValueOps::Smax
+        | ValueOps::Smin
+        | ValueOps::Shl
+        | ValueOps::Shr,
       dest,
       op_type,
       args,
@@ -194,24 +202,13 @@ fn type_check_instruction<'a>(
       update_env(env, dest, op_type)
     }
     Instruction::Value {
-      op: ValueOps::Smax | ValueOps::Smin,
-      dest,
-      op_type,
-      args,
-      funcs,
-      labels,
-      pos: _,
-    } => {
-      check_num_args(2, args)?;
-      check_num_funcs(0, funcs)?;
-      check_num_labels(0, labels)?;
-      check_asmt_type(&Type::Int, get_type(env, 0, args)?)?;
-      check_asmt_type(&Type::Int, get_type(env, 1, args)?)?;
-      check_asmt_type(&Type::Int, op_type)?;
-      update_env(env, dest, op_type)
-    }
-    Instruction::Value {
-      op: ValueOps::Fadd | ValueOps::Fsub | ValueOps::Fmul | ValueOps::Fdiv,
+      op:
+        ValueOps::Fadd
+        | ValueOps::Fsub
+        | ValueOps::Fmul
+        | ValueOps::Fdiv
+        | ValueOps::Fmax
+        | ValueOps::Fmin,
       dest,
       op_type,
       args,
@@ -244,23 +241,6 @@ fn type_check_instruction<'a>(
       check_asmt_type(&Type::Bool, op_type)?;
       update_env(env, dest, op_type)
     }
-    Instruction::Value {
-      op: ValueOps::Fmax | ValueOps::Fmin,
-      dest,
-      op_type,
-      args,
-      funcs,
-      labels,
-      pos: _,
-    } => {
-      check_num_args(2, args)?;
-      check_num_funcs(0, funcs)?;
-      check_num_labels(0, labels)?;
-      check_asmt_type(&Type::Float, get_type(env, 0, args)?)?;
-      check_asmt_type(&Type::Float, get_type(env, 1, args)?)?;
-      check_asmt_type(&Type::Float, op_type)?;
-      update_env(env, dest, op_type)
-    }
     Instruction::Value {
       op: ValueOps::Ceq | ValueOps::Cge | ValueOps::Clt | ValueOps::Cgt | ValueOps::Cle,
       args,

diff --git a/brilirs/src/interp.rs b/brilirs/src/interp.rs
@@ -326,7 +326,7 @@ fn execute_value_op<T: std::io::Write>(
   use bril_rs::ValueOps::{
     Add, Alloc, And, Call, Ceq, Cge, Cgt, Char2int, Cle, Clt, Div, Eq, Fadd, Fdiv, Feq, Fge, Fgt,
     Fle, Flt, Fmax, Fmin, Fmul, Fsub, Ge, Gt, Id, Int2char, Le, Load, Lt, Mul, Not, Or, Phi,
-    PtrAdd, Select, Smax, Smin, Sub,
+    PtrAdd, Select, Shl, Shr, Smax, Smin, Sub,
   };
   match op {
     Add => {
@@ -414,6 +414,18 @@ fn execute_value_op<T: std::io::Write>(
       let res = if arg0 < arg1 { arg0 } else { arg1 };
       state.env.set(dest, Value::Int(res));
     }
+    Shl => {
+      let arg0 = get_arg::<i64>(&state.env, 0, args);
+      let arg1 = get_arg::<i64>(&state.env, 1, args);
+      let res = arg0 << arg1;
+      state.env.set(dest, Value::Int(res));
+    }
+    Shr => {
+      let arg0 = get_arg::<i64>(&state.env, 0, args);
+      let arg1 = get_arg::<i64>(&state.env, 1, args);
+      let res = arg0 >> arg1;
+      state.env.set(dest, Value::Int(res));
+    }
     Fadd => {
       let arg0 = get_arg::<f64>(&state.env, 0, args);
       let arg1 = get_arg::<f64>(&state.env, 1, args);