preliminary support for VAR-SOM-MX7 Cortex-M4

examples/var-som-mx7_m4/board.c

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+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include "board.h"
+#include "debug_console_imx.h"
+#include "ccm_imx7d.h"
+#include "rdc.h"
+#include "wdog_imx.h"
+#include "pin_mux.h"
+
+/* Initialize clock. */
+void BOARD_ClockInit(void)
+{
+    /* OSC/PLL is already initialized by Cortex-A7 (u-boot) */
+
+    /* 
+     * Disable WDOG3 
+     *  Note : The WDOG clock Root is shared by all the 4 WDOGs, so FreeROTS
+     *  code should avoid closing it
+     */
+    CCM_UpdateRoot(CCM, ccmRootWdog, ccmRootmuxWdogOsc24m, 0, 0);
+    CCM_EnableRoot(CCM, ccmRootWdog);
+    CCM_ControlGate(CCM, ccmCcgrGateWdog3, ccmClockNeededRun);
+
+    RDC_SetPdapAccess(RDC, BOARD_WDOG_RDC_PDAP, 3 << (BOARD_DOMAIN_ID * 2), false, false);
+    WDOG_DisablePowerdown(BOARD_WDOG_BASEADDR);
+
+    CCM_ControlGate(CCM, ccmCcgrGateWdog3, ccmClockNotNeeded);
+
+    /* We need system PLL Div2 to run M4 core */
+    CCM_ControlGate(CCM, ccmPllGateSys, ccmClockNeededRun);
+    CCM_ControlGate(CCM, ccmPllGateSysDiv2, ccmClockNeededRun);
+
+    /* Enable clock gate for IP bridge and IO mux */
+    CCM_ControlGate(CCM, ccmCcgrGateIpmux1, ccmClockNeededRun);
+    CCM_ControlGate(CCM, ccmCcgrGateIpmux2, ccmClockNeededRun);
+    CCM_ControlGate(CCM, ccmCcgrGateIpmux3, ccmClockNeededRun);
+    CCM_ControlGate(CCM, ccmCcgrGateIomux, ccmClockNeededRun);
+    CCM_ControlGate(CCM, ccmCcgrGateIomuxLpsr, ccmClockNeededRun);
+
+    /* Enable clock gate for RDC */
+    CCM_ControlGate(CCM, ccmCcgrGateRdc, ccmClockNeededRun);
+}
+
+/* Initialize debug console. */
+void dbg_uart_init(void)
+{
+    /* Set debug uart for M4 core domain access only */
+    RDC_SetPdapAccess(RDC, BOARD_DEBUG_UART_RDC_PDAP, 3 << (BOARD_DOMAIN_ID * 2), false, false);
+
+    /* Select board debug clock derived from OSC clock(24M) */
+    CCM_UpdateRoot(CCM, BOARD_DEBUG_UART_CCM_ROOT, ccmRootmuxUartOsc24m, 0, 0);
+    /* Enable debug uart clock */
+    CCM_EnableRoot(CCM, BOARD_DEBUG_UART_CCM_ROOT);
+    /*
+     * IC Limitation
+     * M4 stop will cause A7 UART lose functionality
+     * So we need UART clock all the time
+     */
+    CCM_ControlGate(CCM, BOARD_DEBUG_UART_CCM_CCGR, ccmClockNeededAll);
+
+    /* Config debug uart pins */
+    configure_uart_pins(BOARD_DEBUG_UART_BASEADDR);
+
+    DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, get_uart_clock_freq(BOARD_DEBUG_UART_BASEADDR), 115200);
+}
+
+void BOARD_RdcInit(void)
+{
+    /* Move M4 core to specific RDC domain */
+    RDC_SetDomainID(RDC, rdcMdaM4, BOARD_DOMAIN_ID, false);
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/

examples/var-som-mx7_m4/board.h

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+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__BOARD_H__)
+#define __BOARD_H__
+
+#include "pin_mux.h"
+#include "rdc.h"
+#include "rdc_defs_imx7d.h"
+#include "ccm_imx7d.h"
+#include "clock_freq.h"
+
+/* The board name */
+#define BOARD_NAME                            "VAR-SOM-MX7_M4"
+#define BOARD_DOMAIN_ID                       (1)
+
+/* ADC information for this board */
+#define BOARD_ADC_RDC_PDAP                    rdcPdapAdc1
+#define BOARD_ADC_CCM_CCGR                    ccmCcgrGateAdc
+#define BOARD_ADC_BASEADDR                    ADC1
+#define BOARD_ADC_IRQ_NUM                     ADC1_IRQn
+#define BOARD_ADC_HANDLER                     ADC1_Handler
+#define BOARD_ADC_INPUT_CHANNEL               (3)
+
+/* WDOG information for this board */
+#define BOARD_WDOG_RDC_PDAP                   rdcPdapWdog3
+#define BOARD_WDOG_CCM_ROOT                   ccmRootWdog
+#define BOARD_WDOG_CCM_CCGR                   ccmCcgrGateWdog3
+#define BOARD_WDOG_BASEADDR                   WDOG3
+#define BOARD_WDOG_IRQ_NUM                    WDOG3_IRQn
+#define BOARD_WDOG_HANDLER                    WDOG3_Handler
+
+/* SEMA4 information for this board */
+#define BOARD_SEMA4_RDC_PDAP                  rdcPdapSemaphoreHs
+#define BOARD_SEMA4_CCM_CCGR                  ccmCcgrGateSemaHs
+#define BOARD_SEMA4_BASEADDR                  SEMA4
+#define BOARD_SEMA4_IRQ_NUM                   SEMA4_HS_M4_IRQn
+#define BOARD_SEMA4_HANDLER                   SEMA4_HS_M4_Handler
+
+/* GPT instance A information for this board */
+#define BOARD_GPTA_RDC_PDAP                   rdcPdapGpt3
+#define BOARD_GPTA_CCM_ROOT                   ccmRootGpt3
+#define BOARD_GPTA_CCM_CCGR                   ccmCcgrGateGpt3
+#define BOARD_GPTA_BASEADDR                   GPT3
+#define BOARD_GPTA_IRQ_NUM                    GPT3_IRQn
+#define BOARD_GPTA_HANDLER                    GPT3_Handler
+/* GPT instance B information for this board */
+#define BOARD_GPTB_RDC_PDAP                   rdcPdapGpt4
+#define BOARD_GPTB_CCM_ROOT                   ccmRootGpt4
+#define BOARD_GPTB_CCM_CCGR                   ccmCcgrGateGpt4
+#define BOARD_GPTB_BASEADDR                   GPT4
+#define BOARD_GPTB_IRQ_NUM                    GPT4_IRQn
+#define BOARD_GPTB_HANDLER                    GPT4_Handler
+
+/* GPIO information for this board */
+#define BOARD_GPIO_LED_CCM_CCGR               ccmCcgrGateGpio1
+#define BOARD_GPIO_LED_RDC_PDAP               rdcPdapGpio1
+#define BOARD_GPIO_LED_CONFIG                 (&gpioLed)
+#define BOARD_GPIO_KEY_CCM_CCGR               ccmCcgrGateGpio1
+#define BOARD_GPIO_KEY_RDC_PDAP               rdcPdapGpio1
+#define BOARD_GPIO_KEY_CONFIG                 (&gpioKeyBack)
+#define BOARD_GPIO_KEY_IRQ_NUM                GPIO1_INT15_0_IRQn
+#define BOARD_GPIO_KEY_HANDLER                GPIO1_INT15_0_Handler
+
+/* Debug UART information for this board */
+#define BOARD_DEBUG_UART_RDC_PDAP             rdcPdapUart2
+#define BOARD_DEBUG_UART_CCM_ROOT             ccmRootUart2
+#define BOARD_DEBUG_UART_CCM_CCGR             ccmCcgrGateUart2
+#define BOARD_DEBUG_UART_BASEADDR             UART2
+#define BOARD_DEBUG_UART_IRQ_NUM              UART2_IRQn
+#define BOARD_DEBUG_UART_HANDLER              UART2_Handler
+
+/* MU information for this board*/
+#define BOARD_MU_HANDLER                      MU_M4_Handler
+#define BOARD_MU_IRQ_NUM                      MU_M4_IRQn
+#define BOARD_MU_BASE_ADDR                    MUB
+#define BOARD_MU_CCM_CCGR                     ccmCcgrGateMu
+#define BOARD_MU_RDC_PDAP                     rdcPdapMuB
+
+/* I2C information for this board */
+#define BOARD_I2C_RDC_PDAP                    rdcPdapI2c2
+#define BOARD_I2C_CCM_ROOT                    ccmRootI2c2
+#define BOARD_I2C_CCM_CCGR                    ccmCcgrGateI2c2
+#define BOARD_I2C_BASEADDR                    I2C2
+#define BOARD_I2C_IRQ_NUM                     I2C2_IRQn
+#define BOARD_I2C_HANDLER                     I2C2_Handler
+#define BOARD_I2C_ISL12057_ADDR               (0x68)
+
+/* FlexCAN information for this board */
+#define BOARD_FLEXCAN_RDC_PDAP                rdcPdapFlexCan2
+#define BOARD_FLEXCAN_CCM_ROOT                ccmRootCan2
+#define BOARD_FLEXCAN_CCM_CCGR                ccmCcgrGateCan2
+#define BOARD_FLEXCAN_BASEADDR                CAN2
+#define BOARD_FLEXCAN_IRQ_NUM                 FLEXCAN2_IRQn
+#define BOARD_FLEXCAN_HANDLER                 FLEXCAN2_Handler
+
+/* GPC information for this board*/
+#define BOARD_GPC_BASEADDR                    GPC
+
+/* SIM_WAKEUP CG information*/
+#define BOARD_SIM_WAKEUP_CCGR                 ccmCcgrGateSimWakeup
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+void hardware_init(void);
+void dbg_uart_init(void);
+/* Function to initialize clock base on board configuration. */
+void BOARD_ClockInit(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* __BOARD_H__ */