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imx93-var-som: Update *_CLOCK_GATE macros
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- *_CLOCK_GATE macros of uart, flexcan, lpi2c, lpspi and lpuart are updated to their correct numbers

Signed-off-by: Andre Morishita <[email protected]>
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morishitaandre committed Aug 14, 2024
1 parent 4da5978 commit 78afa00
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Showing 79 changed files with 79 additions and 79 deletions.
2 changes: 1 addition & 1 deletion boards/som_mx93/demo_apps/ethosu_apps_rpmsg/board.h
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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2 changes: 1 addition & 1 deletion boards/som_mx93/demo_apps/hello_world/board.h
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define USE_CANFD (1)

#define FLEXCAN_CLOCK_ROOT kCLOCK_Root_Can1
#define FLEXCAN_CLOCK_GATE kCLOCK_Can2
#define FLEXCAN_CLOCK_GATE kCLOCK_Can1
#define EXAMPLE_CAN_CLK_FREQ CLOCK_GetIpFreq(FLEXCAN_CLOCK_ROOT)
#define USE_IMPROVED_TIMING_CONFIG (1U)
/* Fix MISRA_C-2012 Rule 17.7. */
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2 changes: 1 addition & 1 deletion boards/som_mx93/driver_examples/canfd/loopback/board.h
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define USE_CANFD (1)

#define FLEXCAN_CLOCK_ROOT kCLOCK_Root_Can1
#define FLEXCAN_CLOCK_GATE kCLOCK_Can2
#define FLEXCAN_CLOCK_GATE kCLOCK_Can1
#define EXAMPLE_CAN_CLK_FREQ CLOCK_GetIpFreq(FLEXCAN_CLOCK_ROOT)
#define USE_IMPROVED_TIMING_CONFIG (1U)
/* Fix MISRA_C-2012 Rule 17.7. */
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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2 changes: 1 addition & 1 deletion boards/som_mx93/driver_examples/edma4/channel_link/board.h
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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2 changes: 1 addition & 1 deletion boards/som_mx93/driver_examples/edma4/memset/board.h
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define TX_MESSAGE_BUFFER_NUM (0)

#define FLEXCAN_CLOCK_ROOT kCLOCK_Root_Can1
#define FLEXCAN_CLOCK_GATE kCLOCK_Can2
#define FLEXCAN_CLOCK_GATE kCLOCK_Can1
#define EXAMPLE_CAN_CLK_FREQ CLOCK_GetIpFreq(FLEXCAN_CLOCK_ROOT)

#define USE_IMPROVED_TIMING_CONFIG (1U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define TX_MESSAGE_BUFFER_NUM (8)

#define FLEXCAN_CLOCK_ROOT kCLOCK_Root_Can1
#define FLEXCAN_CLOCK_GATE kCLOCK_Can2
#define FLEXCAN_CLOCK_GATE kCLOCK_Can1
#define EXAMPLE_CAN_CLK_FREQ CLOCK_GetIpFreq(FLEXCAN_CLOCK_ROOT)
#define USE_IMPROVED_TIMING_CONFIG (1U)
/* Fix MISRA_C-2012 Rule 17.7. */
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2 changes: 1 addition & 1 deletion boards/som_mx93/driver_examples/flexcan/loopback/board.h
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define TX_MESSAGE_BUFFER_NUM (0)

#define FLEXCAN_CLOCK_ROOT kCLOCK_Root_Can1
#define FLEXCAN_CLOCK_GATE kCLOCK_Can2
#define FLEXCAN_CLOCK_GATE kCLOCK_Can1
#define EXAMPLE_CAN_CLK_FREQ (CLOCK_GetIpFreq(FLEXCAN_CLOCK_ROOT))
/* Set USE_IMPROVED_TIMING_CONFIG macro to use api to calculates the improved CAN / CAN FD timing values. */
#define USE_IMPROVED_TIMING_CONFIG (1U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define TX_MESSAGE_BUFFER_NUM (8U)

#define FLEXCAN_CLOCK_ROOT kCLOCK_Root_Can1
#define FLEXCAN_CLOCK_GATE kCLOCK_Can2
#define FLEXCAN_CLOCK_GATE kCLOCK_Can1
#define EXAMPLE_CAN_CLK_FREQ CLOCK_GetIpFreq(FLEXCAN_CLOCK_ROOT)
#define USE_IMPROVED_TIMING_CONFIG (1U)
/* Fix MISRA_C-2012 Rule 17.7. */
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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******************************************************************************/
#define EXAMPLE_I2C_MASTER_BASE (LPI2C7_BASE)
#define LPI2C_MASTER_CLOCK_ROOT kCLOCK_Root_Lpi2c7
#define LPI2C_MASTER_CLOCK_GATE kCLOCK_Lpi2c1
#define LPI2C_MASTER_CLOCK_GATE kCLOCK_Lpi2c7
#define LPI2C_MASTER_CLOCK_FREQUENCY CLOCK_GetIpFreq(LPI2C_MASTER_CLOCK_ROOT)
#define WAIT_TIME 10U

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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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******************************************************************************/
#define EXAMPLE_I2C_SLAVE_BASE (LPI2C7_BASE)
#define LPI2C_SLAVE_CLOCK_ROOT kCLOCK_Root_Lpi2c7
#define LPI2C_SLAVE_CLOCK_GATE kCLOCK_Lpi2c1
#define LPI2C_SLAVE_CLOCK_GATE kCLOCK_Lpi2c7
#define LPI2C_SLAVE_CLOCK_FREQUENCY CLOCK_GetIpFreq(LPI2C_SLAVE_CLOCK_ROOT)

#define EXAMPLE_I2C_SLAVE ((LPI2C_Type *)EXAMPLE_I2C_SLAVE_BASE)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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******************************************************************************/
#define EXAMPLE_I2C_MASTER_BASE (LPI2C7_BASE)
#define LPI2C_MASTER_CLOCK_ROOT kCLOCK_Root_Lpi2c7
#define LPI2C_MASTER_CLOCK_GATE kCLOCK_Lpi2c1
#define LPI2C_MASTER_CLOCK_GATE kCLOCK_Lpi2c7
#define LPI2C_MASTER_CLOCK_FREQUENCY CLOCK_GetIpFreq(LPI2C_MASTER_CLOCK_ROOT)
#define WAIT_TIME 10U

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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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******************************************************************************/
#define EXAMPLE_I2C_SLAVE_BASE (LPI2C7_BASE)
#define LPI2C_SLAVE_CLOCK_ROOT kCLOCK_Root_Lpi2c7
#define LPI2C_SLAVE_CLOCK_GATE kCLOCK_Lpi2c1
#define LPI2C_SLAVE_CLOCK_GATE kCLOCK_Lpi2c7
#define LPI2C_SLAVE_CLOCK_FREQUENCY CLOCK_GetIpFreq(LPI2C_SLAVE_CLOCK_ROOT)

#define EXAMPLE_I2C_SLAVE ((LPI2C_Type *)EXAMPLE_I2C_SLAVE_BASE)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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******************************************************************************/
#define EXAMPLE_LPSPI_MASTER_BASEADDR LPSPI6
#define LPSPI_MASTER_CLOCK_ROOT kCLOCK_Root_Lpspi6
#define LPSPI_MASTER_CLOCK_GATE kCLOCK_Lpspi3
#define LPSPI_MASTER_CLOCK_GATE kCLOCK_Lpspi6
#define LPSPI_MASTER_CLK_FREQ (CLOCK_GetIpFreq(LPSPI_MASTER_CLOCK_ROOT))
#define EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT kLPSPI_Pcs0
#define EXAMPLE_LPSPI_MASTER_PCS_FOR_TRANSFER kLPSPI_MasterPcs0
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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#define EXAMPLE_LPSPI_SLAVE_CLOCK_NAME (LPSPI_SLAVE_CLOCK_ROOT)
#define LPSPI_SLAVE_CLOCK_ROOT kCLOCK_Root_Lpspi6
#define LPSPI_SLAVE_CLOCK_GATE kCLOCK_Lpspi3
#define LPSPI_SLAVE_CLOCK_GATE kCLOCK_Lpspi6
#define TRANSFER_SIZE 64U /*! Transfer dataSize */

/*******************************************************************************
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#define BOARD_DEBUG_UART_BAUDRATE 115200U
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart2
#define BOARD_DEBUG_UART_CLOCK_GATE kCLOCK_Lpuart7
#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT)

#define VDEV0_VRING_BASE (0x87ee0000U)
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Expand Up @@ -18,7 +18,7 @@
******************************************************************************/
#define EXAMPLE_LPSPI_MASTER_BASEADDR LPSPI6
#define LPSPI_MASTER_CLOCK_ROOT kCLOCK_Root_Lpspi6
#define LPSPI_MASTER_CLOCK_GATE kCLOCK_Lpspi3
#define LPSPI_MASTER_CLOCK_GATE kCLOCK_Lpspi6
#define LPSPI_MASTER_CLK_FREQ (CLOCK_GetIpFreq(LPSPI_MASTER_CLOCK_ROOT))
#define EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT kLPSPI_Pcs0
#define EXAMPLE_LPSPI_MASTER_PCS_FOR_TRANSFER kLPSPI_MasterPcs0
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