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Add Bender.yml file
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micprog authored and vogelpi committed Jan 21, 2021
1 parent ebc92e8 commit 54becdb
Showing 1 changed file with 40 additions and 0 deletions.
40 changes: 40 additions & 0 deletions Bender.yml
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package:
name: ibex
authors: []

sources:
- include_dirs:
- rtl
- shared/rtl
files:
- rtl/ibex_pkg.sv
- rtl/ibex_alu.sv
- rtl/ibex_compressed_decoder.sv
- rtl/ibex_controller.sv
- rtl/ibex_cs_registers.sv
- rtl/ibex_counters.sv
- rtl/ibex_decoder.sv
- rtl/ibex_ex_block.sv
- rtl/ibex_id_stage.sv
- rtl/ibex_if_stage.sv
- rtl/ibex_wb_stage.sv
- rtl/ibex_load_store_unit.sv
- rtl/ibex_multdiv_slow.sv
- rtl/ibex_multdiv_fast.sv
- rtl/ibex_prefetch_buffer.sv
- rtl/ibex_fetch_fifo.sv
- rtl/ibex_pmp.sv
- rtl/ibex_core.sv
- shared/rtl/prim_assert.sv
- target: rtl
files:
- rtl/ibex_pkg.sv
- rtl/ibex_tracer_pkg.sv
- rtl/ibex_tracer.sv
- rtl/ibex_core_tracing.sv
- target: all(rtl, tsmc55, gf22)
files:
- rtl/ibex_register_file_latch.sv
- target: all(xilinx)
files:
- rtl/ibex_register_file_fpga.sv

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