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op-mode: T6715: manually changing time/date is not synced into hardware clock (backport #4071) #4074

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merged 1 commit into from
Sep 16, 2024

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@mergify mergify bot commented Sep 16, 2024

Change Summary

When not using NTP and adjusting the current system time/date using set date the time is not saved across a reboot into the hardware RTC. This commit explicitly syncs the current time after a change into the systems RTC.

Most routers do not run without NTP (which is even a VyOS default) so the priority is pretty low.

Types of changes

  • Bug fix (non-breaking change which fixes an issue)
  • New feature (non-breaking change which adds functionality)
  • Code style update (formatting, renaming)
  • Refactoring (no functional changes)
  • Migration from an old Vyatta component to vyos-1x, please link to related PR inside obsoleted component
  • Other (please describe):

Related Task(s)

How to test

set date 0916140224

Checklist:

  • I have read the CONTRIBUTING document
  • I have linked this PR to one or more Phabricator Task(s)
  • I have run the components SMOKETESTS if applicable
  • My commit headlines contain a valid Task id
  • My change requires a change to the documentation
  • I have updated the documentation accordingly

This is an automatic backport of pull request #4071 done by [Mergify](https://mergify.com).

…re clock

When not using NTP and adjusting the current system time/date using set date
the time is not saved across a reboot into the hardware RTC. This commit
explicitly syncs the current time after a change into the systems RTC.

Most routers do not run without NTP (which is even a VyOS default) so the
priority is pretty low.

(cherry picked from commit 835126e)
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No issues in PR Title / Commit Title

@sever-sever sever-sever merged commit 7a71f27 into sagitta Sep 16, 2024
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@mergify mergify bot deleted the mergify/bp/sagitta/pr-4071 branch September 16, 2024 17:30
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4 participants