Merge with upstream #270
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Merge with upstream #270
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…nce#9751) * implement trapz for aarch64 * implement call_with_name for aarch64 asm * implement call_with_reg for aarch64 asm * implement call_with_lib for aarch64 asm * tidy imports * implement address_at_vmctx for aarch64 masm * tidy imports * add tests * fmt pass * fix test after rebase * add some comments * pass calling convention down to asm after bytecodealliance#9757 * s/Emits/Emit/ * fix test
Adds a flag that can be used to control the `extended-const` proposal on the CLI.
…tore and not wasmtime_store_t *store (bytecodealliance#9770)
* implement div for aarch64 * add tests * fmt pass * review edits * fmt pass
* Sort tests by name to ensure that a reproduction on one machine works on another. * Relax the error message matching to be a bit more lenient with paths.
* Fix some off-by-one comparisons in assertions Fuzzing found a small issue with bytecodealliance#9687 and this commit relaxes a few off-by-one checks to allow addressing one-byte-beyond-the-end of a linear memory. * Review comments
…9760) * Procedurally generate Pulley Cranelift boilerplate This commit is an integration of the `for_each_op!` macro (and extended ops) for Cranelift. This procedurally generates a few new items for Cranelift's Pulley backend to use: * `RawInst` - a raw enumeration of instructions as-is. * ISLE constructors (e.g. `pulley_*` ctors) - generated for all of the `RawInst` variants. * Register allocation methods for `RawInst` * Pretty printing methods for `RawInst` * Emission methods for `RawInst` The `Inst` enum now has a `Raw` variant which contains a `RawInst`. In this manner the main `Inst` enum can still have pseudo-insts like `Call`, polymorphic instructions like loads/stores (probably gonna get refactored in the future though), and slightly different representations such as `Inst::Trap` having a `TrapCode` and `RawInst::Trap` wouldn't. The goal of this commit is to lower the amount of effort to quickly add and experiment with new instructions in Pulley. Ideally it's now just (a) define them in the pulley macro, (b) implement a direct lowering rule, and (c) implement it in the interpreter. Ideally no need to implement anything else inside of Cranelift as everything should be auto-generated. Many existing `Inst` variants have been deleted in favor of their equivalents in `RawInst` now. This undeniably increases the complexity of the Pulley backend but at least for me I find it well worth it to have all this boilerplate generated automatically. * Fill out TODO * Fix conditional generation of pulley ISLE
Tune `memory_reservation_for_growth` automatically when malloc-based memories are used to avoid hitting OOM conditions.
…liance#9769) Use the new `Encode` trait to improve the `pc_rel_jump` helper.
Nothing big here, just a bump to the latest version of `arbitrary` to stay up to date.
Added Huawei Cloud as one of the adopters of Wasmtime.
* Add a guide for adding instructions to Pulley In helping others contribute to Pulley I've written up the steps I took to make this commit itself. I've picked a random test in `misc_testsuite` that previously didn't work on Pulley and was relatively small. I implemented a few lowerings and some new instructions and now the test passes. I've added `pulley/CONTRIBUTING.md` to document the experience along the way in case anyone else is interested to help out in the future. * Fix fuzzer build * Review comments * Fix pulley test * Fix no_std build * Fix fuzz simple push pop in miri
* pulley: Implement more of loads/stores This commit gets the `address.wast` spec test working by filling out more load/store infrastructure in Pulley. In doing so I've done a refactoring of the existing load/store methods. Changes here are: * All load/stores are `*_offset32` now instead of optionally having no offset, a 8-bit offset, or a 64-bit offset. * All x-register loads/stores are prefixed with `x` now. * All loads/stores have "le" for little-endian in their name. * Loads/stores are refactored to have 8 and 16-bit variants. * Sign-extending loads now either extend to 32 or 64 depending on the opcode. * Float loads/stores are added. * Big-endian is handled with explicit big-endian loads/stores instead `bswap` to handle this transparently in the backend (e.g. for stores not ISLE-generated) and to handle floats. * Remove pulley interpreter fuzz target This is a bit onerous to keep updated and is probably best subsumed by the fuzzing support we have in general for wasm. * Update pulley tests * Fixes from a rebase * Review comments * Update test expectations
…nce#9778) * Wasmtime: support a notion of "custom code publisher". In some `no_std` environments, virtual memory usage is *generally* prohibited for performance-predictability reasons, but the MMU hardware is still in use for permissions (e.g., `W^X` write-xor-execute). Occasional changes to page mapping permissions are thus necessary when new modules are loaded dynamically, and are acceptable in that context. Wasmtime needs a way to support "publishing" code (making it executable) in such environments. Rather than try to segment the `signals-based-traps` divide further, and piece out the code-publishing parts from the heap parts, and backdoor a path to `mprotect` in an otherwise `no_std` build, in this PR I have opted to add a trait an impl of which the embedder can provide to the `Config` to implement custom actions for "code publish". This otherwise operates properly in a no-`signals-based-traps` environment, e.g., the module backing memory itself is regularly allocated rather than mmap'd (but is now aligned to the degree requested by the trait impl). * Review feedback. * Plumb through custom alignment for runtime code generation * Add a test for custom code memory.
…9779) * pulley: Ungate SIMD proposal to enable more tests This commit removes the simd proposal from "known panicking compiler features" for Pulley by filling out some minor ABI bits around loads/stores of v128 in the Cranelift ABI code. This unlocks running `spec_testsuite/*.wast` in CI and expecting it to pass as otherwise everything was rejected since that test suite requires SIMD and it never even got to the Cranelift backend. This then fixes a few minor issues here and there to get existing tests passing now that they're actually being run. Some examples are: * Fix some copy/paste typos around callee-save clobbers and float registers. * Add vector load/store support to avoid panicking in ABI code (not well tested yet though). * Zero-extend the condition in `brif`'s lowering to ensure that the entire register is defined. In the future more variants of `br_if` in Pulley are probably desired. * Limit `store` lowerings to just integer types, not vector types. * Fix `Func::call` with Pulley when the callee is a host function. * Fix test expectations prtest:full
* pulley: Ungate memory64 feature This commit is similar to bytecodealliance#9779 in that it's removing a proposal from the "known list of panicking features" for Pulley to allow more tests to run on Pulley. This then fills out a few miscellaneous instructions to get a full suite of tests passing in Pulley related to memory64 and other instructions. prtest:full * Add notes about spectre speculation
This commit fixes how signedness division is hanlded in aarch64. Prior to this commit, sign-extension was emitted unconditionally. This commit ensures that the correct extension is emitted depending on the division kind. Additionally this commit prefers making use of existing assembler helpers.
* pulley: Ungate the `GC_TYPES` feature from Pulley Similar to bytecodealliance#9779 this remove the `GC_TYPES` feature from the list of panicking features in Pulley. In doing so this then additionally fixes a number of panics and then adds more tests that are working. Some other minor instructions are filled out to ensure that tests are working on both 32 and 64-bit platforms. * Flag test as now passing
…ce#9786) With enough basic support here and there switch the listing of tests for Pulley from known-passing to known-failing instead. This trims the list of unsupported features to just those that are truly unsupported and then additionally rewrites the list of tests to be an exhasutive list of unsupported tests instead of a list of supported tests. This should make it a bit easier to track the progress as now pulley is "complete" once this list is empty.
* pulley: Get `align.wast` passing Required implementing lowerings for `f32const` and `f64const` CLIF instructions which then also got a number of other tests passing. * Undo winch change
* implement copy/clone for RemKind * implement remainder operation for aarch64 * add tests * fmt pass * review edits
Filling out float compares and some miscellaneous bit-related integer instructions.
This commit fills in the `load_addr` Masm implementation. `load_addr` is mostly used for multi-value. This commit introduces some disas tests as well.
* pulley: More division/remainder instructions Gets a few misc tests passing * Review comments
…9787) * winch Aarch64: fix reinterpret instructions * winch Aarch64: implement signed_convert and unsigned_convert
This commit adds a `debug.rs` to Pulley to print out the instruction being executed and the state of all registers between instructions. This is turned off by default and does not have a runtime or environment-based configuration value. Instead changing this requires changing source code for now. This enables the interpreter loop to unconditionally use this "debugger" where it'll compile away to nothing in release/benchmarking situations. This commit additionally adds this support to the `tail_loop` module and fixes a few issues there such as it accidentally not being tested in CI as well as a new `#[cfg]` to use it on stable rust with normal `return` under the assumption that LLVM is highly likely to do TCO.
* pulley: Flesh out conditional registers This commit redefines previous Pulley instructions working with conditional values and results to always operate on the low 32-bits of a register rather than the full 64-bit width of integer registers. This should help 32-bit platforms work with just a word and avoid an extraneous load of top bits that are likely always zero. The previous `br_if` and `br_if_not` instructions now have a "32" suffix to make it clear that they're only operating on 32-bit register widths. Additionally the `xeq32` family of instructions (compare-and-set) now all only define the low 32-bits of the destination register. Finally, lowerings of `select` in CLIF were added for integer and floating-point registers. cc bytecodealliance#9783 * Fix interpreter tests
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