cleanup: overload extra_args for brevity and less magic int literals,…

… fixes opt_demorgan warning
widlarizer · Apr 2, 2024 · 030d478 · 030d478
1 parent 7159a98
commit 030d478
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Showing 57 changed files with 66 additions and 247 deletions.
diff --git a/kernel/register.cc b/kernel/register.cc
@@ -210,6 +210,11 @@ void Pass::cmd_error(const std::vector<std::string> &args, size_t argidx, std::s
 			msg.c_str(), command_text.c_str(), error_pos, "");
 }
 
+void Pass::extra_args(std::vector<std::string> args, RTLIL::Design *design)
+{
+	extra_args(args, 1, design, false);
+}
+
 void Pass::extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Design *design, bool select)
 {
 	for (; argidx < args.size(); argidx++)

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
@@ -1478,8 +1478,7 @@ struct ShellPass : public Pass {
 		log("Press Ctrl-D or type 'exit' to leave the interactive shell.\n");
 		log("\n");
 	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
-		extra_args(args, 1, design, false);
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override {		extra_args(args, design);
 		shell(design);
 	}
 } ShellPass;
@@ -1496,8 +1495,7 @@ struct HistoryPass : public Pass {
 		log("from executed scripts.\n");
 		log("\n");
 	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
-		extra_args(args, 1, design, false);
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override {		extra_args(args, design);
 #ifdef YOSYS_ENABLE_READLINE
 		for(HIST_ENTRY **list = history_list(); *list != NULL; list++)
 			log("%s\n", (*list)->line);

diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc
@@ -100,8 +100,7 @@ struct AutonamePass : public Pass {
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
-	{
-		extra_args(args, 1, design);
+	{		extra_args(args, design);
 
 		log_header(design, "Executing AUTONAME pass.\n");
 

diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc
@@ -35,8 +35,7 @@ struct BlackboxPass : public Pass {
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
-	{
-		extra_args(args, 1, design);
+	{		extra_args(args, design);
 
 		for (auto module : design->selected_whole_modules_warn(true))
 		{

diff --git a/passes/cmds/clean_zerowidth.cc b/passes/cmds/clean_zerowidth.cc
@@ -51,8 +51,7 @@ struct CleanZeroWidthPass : public Pass {
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
-	{
-		extra_args(args, 1, design);
+	{		extra_args(args, design);
 
 		CellTypes ct;
 		ct.setup();

diff --git a/passes/cmds/future.cc b/passes/cmds/future.cc
@@ -122,14 +122,7 @@ struct FuturePass : public Pass {
 		FutureOptions options;
 
 		log_header(design, "Executing FUTURE pass.\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-
-			break;
-		}
-
-		extra_args(args, argidx, design);
+		extra_args(args, design);
 
 		for (auto module : design->selected_modules()) {
 			FutureWorker worker(module, options);

diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc
@@ -49,9 +49,7 @@ struct PrintAttrsPass : public Pass {
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
-	{
-		size_t argidx = 1;
-		extra_args(args, argidx, design);
+	{		extra_args(args, design);
 
 		unsigned int indent = 0;
 		for (auto mod : design->selected_modules())

diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
@@ -43,8 +43,7 @@ struct ScatterPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		CellTypes ct(design);
-		extra_args(args, 1, design);
+		CellTypes ct(design);		extra_args(args, design);
 
 		for (auto module : design->selected_modules())
 		{

diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
@@ -1712,9 +1712,7 @@ struct LsPass : public Pass {
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
-	{
-		size_t argidx = 1;
-		extra_args(args, argidx, design);
+	{		extra_args(args, design);
 
 		if (design->selected_active_module.empty())
 		{

diff --git a/passes/cmds/sta.cc b/passes/cmds/sta.cc
@@ -289,17 +289,8 @@ struct StaPass : public Pass {
 	{
 		log_header(design, "Executing STA pass (static timing analysis).\n");
 
-		/*
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			if (args[argidx] == "-TODO") {
-				continue;
-			}
-			break;
-		}
-		*/
-
-		extra_args(args, 1, design);
+		// TODO: there was a commented out -TODO argument
+		extra_args(args, design);
 
 		for (Module *module : design->selected_modules())
 		{

diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc
@@ -219,12 +219,7 @@ struct EquivMarkPass : public Pass {
 	void execute(std::vector<std::string> args, Design *design) override
 	{
 		log_header(design, "Executing EQUIV_MARK pass.\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, design);
 
 		for (auto module : design->selected_whole_modules_warn()) {
 			EquivMarkWorker worker(module);

diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc
@@ -190,12 +190,7 @@ struct EquivPurgePass : public Pass {
 	void execute(std::vector<std::string> args, Design *design) override
 	{
 		log_header(design, "Executing EQUIV_PURGE pass.\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, design);
 
 		for (auto module : design->selected_whole_modules_warn()) {
 			EquivPurgeWorker worker(module);

diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
@@ -419,8 +419,7 @@ struct FsmExtractPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");
-		extra_args(args, 1, design);
+		log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");		extra_args(args, design);
 
 		CellTypes ct(design);
 

diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc
@@ -43,8 +43,7 @@ struct FsmInfoPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
-		extra_args(args, 1, design);
+		log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");		extra_args(args, design);
 
 		for (auto mod : design->selected_modules())
 			for (auto cell : mod->selected_cells())

diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
@@ -333,8 +333,7 @@ struct FsmMapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
-		extra_args(args, 1, design);
+		log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");		extra_args(args, design);
 
 		for (auto mod : design->selected_modules()) {
 			std::vector<RTLIL::Cell*> fsm_cells;

diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc
@@ -337,8 +337,7 @@ struct FsmOptPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");
-		extra_args(args, 1, design);
+		log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");		extra_args(args, design);
 
 		for (auto mod : design->selected_modules())
 			for (auto cell : mod->selected_cells())

diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc
@@ -44,17 +44,7 @@ struct UniquifyPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing UNIQUIFY pass (creating unique copies of modules).\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			// if (args[argidx] == "-check") {
-			// 	flag_check = true;
-			// 	continue;
-			// }
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, design);
 
 		bool did_something = true;
 		int count = 0;

diff --git a/passes/memory/memory_bmux2rom.cc b/passes/memory/memory_bmux2rom.cc
@@ -38,12 +38,7 @@ struct MemoryBmux2RomPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, design);
 
 		for (auto module : design->selected_modules()) {
 			for (auto cell : module->selected_cells()) {

diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
@@ -36,8 +36,7 @@ struct MemoryCollectPass : public Pass {
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
-		log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
-		extra_args(args, 1, design);
+		log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");		extra_args(args, design);
 		for (auto module : design->selected_modules()) {
 			if (module->has_processes_warn())
 				continue;

diff --git a/passes/memory/memory_memx.cc b/passes/memory/memory_memx.cc
@@ -50,8 +50,7 @@ struct MemoryMemxPass : public Pass {
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
-		log_header(design, "Executing MEMORY_MEMX pass (emit soft logic for out-of-bounds handling).\n");
-		extra_args(args, 1, design);
+		log_header(design, "Executing MEMORY_MEMX pass (emit soft logic for out-of-bounds handling).\n");		extra_args(args, design);
 
 		for (auto module : design->selected_modules())
 		for (auto &mem : Mem::get_selected_memories(module))

diff --git a/passes/memory/memory_narrow.cc b/passes/memory/memory_narrow.cc
@@ -38,12 +38,7 @@ struct MemoryNarrowPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing MEMORY_NARROW pass (splitting up wide memory ports).\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, design);
 
 		for (auto module : design->selected_modules()) {
 			if (module->has_processes_warn())

diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
@@ -36,8 +36,7 @@ struct MemoryUnpackPass : public Pass {
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
-		log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
-		extra_args(args, 1, design);
+		log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");		extra_args(args, design);
 		for (auto module : design->selected_modules()) {
 			for (auto &mem : Mem::get_selected_memories(module)) {
 				if (mem.packed) {

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
@@ -344,8 +344,7 @@ struct MuxpackPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing MUXPACK pass ($mux cell cascades to $pmux).\n");
-
-		extra_args(args, 1, design);
+		extra_args(args, design);
 
 		int mux_count = 0;
 		int pmux_count = 0;

diff --git a/passes/opt/opt_demorgan.cc b/passes/opt/opt_demorgan.cc
@@ -182,9 +182,7 @@ struct OptDemorganPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing OPT_DEMORGAN pass (push inverters through $reduce_* cells).\n");
-
-		int argidx = 0;
-		extra_args(args, argidx, design);
+		extra_args(args, design);
 
 		unsigned int cells_changed = 0;
 		for (auto module : design->selected_modules())

diff --git a/passes/opt/opt_ffinv.cc b/passes/opt/opt_ffinv.cc
@@ -246,8 +246,7 @@ struct OptFfInvPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing OPT_FFINV pass (push inverters through FFs).\n");
-
-		extra_args(args, 1, design);
+		extra_args(args, design);
 
 		int total_count = 0;
 		for (auto module : design->selected_modules())

diff --git a/passes/opt/opt_mem_feedback.cc b/passes/opt/opt_mem_feedback.cc
@@ -337,8 +337,7 @@ struct OptMemFeedbackPass : public Pass {
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
-		log_header(design, "Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n");
-		extra_args(args, 1, design);
+		log_header(design, "Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n");		extra_args(args, design);
 		OptMemFeedbackWorker worker(design);
 
 		for (auto module : design->selected_modules())

diff --git a/passes/opt/opt_mem_priority.cc b/passes/opt/opt_mem_priority.cc
@@ -41,8 +41,7 @@ struct OptMemPriorityPass : public Pass {
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
-		log_header(design, "Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n");
-		extra_args(args, 1, design);
+		log_header(design, "Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n");		extra_args(args, design);
 
 		ModWalker modwalker(design);
 

diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
@@ -487,8 +487,7 @@ struct OptMuxtreePass : public Pass {
 	}
 	void execute(vector<std::string> args, RTLIL::Design *design) override
 	{
-		log_header(design, "Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");
-		extra_args(args, 1, design);
+		log_header(design, "Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");		extra_args(args, design);
 
 		int total_count = 0;
 		for (auto module : design->selected_whole_modules_warn()) {

diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
@@ -356,8 +356,7 @@ struct OptSharePass : public Pass {
 	{
 
 		log_header(design, "Executing OPT_SHARE pass.\n");
-
-		extra_args(args, 1, design);
+		extra_args(args, design);
 		for (auto module : design->selected_modules()) {
 			SigMap sigmap(module);
 

diff --git a/passes/opt/rmports.cc b/passes/opt/rmports.cc
@@ -42,9 +42,7 @@ struct RmportsPassPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing RMPORTS pass (remove ports with no connections).\n");
-
-		size_t argidx = 1;
-		extra_args(args, argidx, design);
+		extra_args(args, design);
 
 		// The set of ports we removed
 		dict<IdString, pool<IdString>> removed_ports;

diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc
@@ -55,8 +55,7 @@ struct PeepoptPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing PEEPOPT pass (run peephole optimizers).\n");
-
-		extra_args(args, 1, design);
+		extra_args(args, design);
 
 		for (auto module : design->selected_modules())
 		{