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test_cell: add -check_cost and -bloat to increase cell size
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@widlarizer
widlarizer committed May 7, 2024
1 parent 32b1421 commit e5f872e
Showing 1 changed file with 58 additions and 16 deletions.
74 changes: 58 additions & 16 deletions passes/tests/test_cell.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -23,11 +23,13 @@
#include "kernel/consteval.h"
#include "kernel/celledges.h"
#include "kernel/macc.h"
#include "kernel/cost.h"
#include <algorithm>

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

static int bloat_factor = 1;
static uint32_t xorshift32_state = 123456789;

static uint32_t xorshift32(uint32_t limit) {
Expand All @@ -37,15 +39,15 @@ static uint32_t xorshift32(uint32_t limit) {
return xorshift32_state % limit;
}

static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags, bool constmode, bool muxdiv)
static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags, bool constmode, bool muxdiv)
{
RTLIL::Module *module = design->addModule(ID(gold));
RTLIL::Cell *cell = module->addCell(ID(UUT), cell_type);
RTLIL::Wire *wire;

if (cell_type.in(ID($mux), ID($pmux)))
{
int width = 1 + xorshift32(8);
int width = 1 + xorshift32(8 * bloat_factor);
int swidth = cell_type == ID($mux) ? 1 : 1 + xorshift32(8);

wire = module->addWire(ID::A);
Expand All @@ -71,8 +73,8 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,

if (cell_type == ID($bmux))
{
int width = 1 + xorshift32(8);
int swidth = 1 + xorshift32(4);
int width = 1 + xorshift32(8 * bloat_factor);
int swidth = 1 + xorshift32(4 * bloat_factor);

wire = module->addWire(ID::A);
wire->width = width << swidth;
Expand All @@ -92,8 +94,8 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,

if (cell_type == ID($demux))
{
int width = 1 + xorshift32(8);
int swidth = 1 + xorshift32(6);
int width = 1 + xorshift32(8 * bloat_factor);
int swidth = 1 + xorshift32(6 * bloat_factor);

wire = module->addWire(ID::A);
wire->width = width;
Expand All @@ -113,7 +115,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,

if (cell_type == ID($fa))
{
int width = 1 + xorshift32(8);
int width = 1 + xorshift32(8 * bloat_factor);

wire = module->addWire(ID::A);
wire->width = width;
Expand Down Expand Up @@ -143,7 +145,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,

if (cell_type == ID($lcu))
{
int width = 1 + xorshift32(8);
int width = 1 + xorshift32(8 * bloat_factor);

wire = module->addWire(ID::P);
wire->width = width;
Expand All @@ -168,7 +170,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
if (cell_type == ID($macc))
{
Macc macc;
int width = 1 + xorshift32(8);
int width = 1 + xorshift32(8 * bloat_factor);
int depth = 1 + xorshift32(6);
int mulbits_a = 0, mulbits_b = 0;

Expand Down Expand Up @@ -215,7 +217,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,

if (cell_type == ID($lut))
{
int width = 1 + xorshift32(6);
int width = 1 + xorshift32(6 * bloat_factor);

wire = module->addWire(ID::A);
wire->width = width;
Expand All @@ -235,7 +237,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,

if (cell_type == ID($sop))
{
int width = 1 + xorshift32(8);
int width = 1 + xorshift32(8 * bloat_factor);
int depth = 1 + xorshift32(8);

wire = module->addWire(ID::A);
Expand Down Expand Up @@ -270,17 +272,17 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,

if (cell_type_flags.find('A') != std::string::npos) {
wire = module->addWire(ID::A);
wire->width = 1 + xorshift32(8);
wire->width = 1 + xorshift32(8 * bloat_factor);
wire->port_input = true;
cell->setPort(ID::A, wire);
}

if (cell_type_flags.find('B') != std::string::npos) {
wire = module->addWire(ID::B);
if (cell_type_flags.find('h') != std::string::npos)
wire->width = 1 + xorshift32(6);
wire->width = 1 + xorshift32(6 * bloat_factor);
else
wire->width = 1 + xorshift32(8);
wire->width = 1 + xorshift32(8 * bloat_factor);
wire->port_input = true;
cell->setPort(ID::B, wire);
}
Expand All @@ -301,7 +303,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,

if (cell_type_flags.find('Y') != std::string::npos) {
wire = module->addWire(ID::Y);
wire->width = 1 + xorshift32(8);
wire->width = 1 + xorshift32(8 * bloat_factor);
wire->port_output = true;
cell->setPort(ID::Y, wire);
}
Expand Down Expand Up @@ -380,6 +382,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
module->fixup_ports();
cell->fixup_parameters();
cell->check();
return cell;
}

static void run_edges_test(RTLIL::Design *design, bool verbose)
Expand Down Expand Up @@ -760,6 +763,11 @@ struct TestCellPass : public Pass {
log("\n");
log(" -vlog {filename}\n");
log(" create a Verilog test bench to test simlib and write_verilog\n");
log(" -bloat {factor}\n");
log(" increase cell size limits b{factor} times where possible\n");
log(" -check_cost\n");
log(" check the estimated cell cost is a valid upper bound for the techmapped\n");
log(" cell count \n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design*) override
Expand All @@ -775,6 +783,7 @@ struct TestCellPass : public Pass {
bool nosat = false;
bool noeval = false;
bool edges = false;
bool check_cost = false;

int argidx;
for (argidx = 1; argidx < GetSize(args); argidx++)
Expand Down Expand Up @@ -842,6 +851,14 @@ struct TestCellPass : public Pass {
log_cmd_error("Failed to open output file `%s'.\n", args[argidx].c_str());
continue;
}
if (args[argidx] == "-bloat" && argidx+1 < GetSize(args)) {
bloat_factor = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-check_cost") {
check_cost = true;
continue;
}
break;
}

Expand Down Expand Up @@ -968,11 +985,12 @@ struct TestCellPass : public Pass {
for (auto cell_type : selected_cell_types)
for (int i = 0; i < num_iter; i++)
{
Cell* uut = nullptr;
RTLIL::Design *design = new RTLIL::Design;
if (cell_type == ID(rtlil))
Frontend::frontend_call(design, NULL, std::string(), "rtlil " + rtlil_file);
else
create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv);
uut = create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv);
if (!write_prefix.empty()) {
Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i));
} else if (edges) {
Expand All @@ -997,6 +1015,30 @@ struct TestCellPass : public Pass {
}
if (!noeval)
run_eval_test(design, verbose, nosat, uut_name, vlog_file);
if (check_cost && uut) {
Pass::call(design, "select gate");
int num_cells = 0;
for (auto mod : design->selected_modules()) {
// Expected to run once
for (auto cell : mod->selected_cells()) {
(void) cell;
num_cells++;
}
}
CellCosts costs(CellCosts::DEFAULT, design);
Pass::call(design, "select gold");
for (auto mod : design->selected_modules()) {
log_assert(mod->name.str() == "\\gold");
// Expected to run once
int num_cells_estimate = costs.get(uut);
if (num_cells <= num_cells_estimate) {
// correct
log_debug("Correct upper bound for %s: %d <= %d\n", cell_type.c_str(), num_cells, num_cells_estimate);
} else {
log_warning("Upper bound violated for %s: %d > %d\n", cell_type.c_str(), num_cells, num_cells_estimate);
}
}
}
}
delete design;
}
Expand Down

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