Fix for QUICC Engine. The base address was incorrect (should be 0x140…

…000). Integrity OS is starting up now.
wolfSSL · Dec 29, 2023 · 654ade8 · 654ade8
1 parent 93f97a1
commit 654ade8
Showing 1 changed file with 16 additions and 14 deletions.
diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c
@@ -174,39 +174,38 @@ static void hal_flash_unlock_sector(uint32_t sector);
 #define QE_FW_ADDR   0xEFE00000 /* location in NOR flash */
 #endif
 
-#define QE_BASE                (CCSRBAR + 0xF000)
-#define QE_CEPIER              ((volatile uint32_t*)(QE_BASE + 0x00CUL))
-#define QE_CEPIMR              ((volatile uint32_t*)(QE_BASE + 0x010UL))
-#define QE_CEPICR              ((volatile uint32_t*)(QE_BASE + 0x014UL))
 
-#define QE_ENGINE_BASE         (CCSRBAR + 0x80000)
-#define QE_IRAM_IADD           ((volatile uint32_t*)(QE_ENGINE_BASE + 0x000UL))
-#define QE_IRAM_IDATA          ((volatile uint32_t*)(QE_ENGINE_BASE + 0x004UL))
-#define QE_IRAM_IREADY         ((volatile uint32_t*)(QE_ENGINE_BASE + 0x00CUL))
+#define QE_BASE                (CCSRBAR + 0x140000)
+#define QE_IRAM_IADD           ((volatile uint32_t*)(QE_BASE + 0x000UL))
+#define QE_IRAM_IDATA          ((volatile uint32_t*)(QE_BASE + 0x004UL))
+#define QE_IRAM_IREADY         ((volatile uint32_t*)(QE_BASE + 0x00CUL))
+
+/* QUICC Engine Interrupt Controller */
+#define QEIC_CIMR              ((volatile uint32_t*)(QE_BASE + 0x0A0UL))
 
 /* T1024 -> Two UCCs — UCC1, UCC3 supported - CMX UCC1/3 Clock Route Register */
-#define QE_CMXUCR1             ((volatile uint32_t*)(QE_ENGINE_BASE + 0xC0000 + 0x410UL))
+#define QE_CMXUCR1             ((volatile uint32_t*)(QE_BASE + 0xC0000 + 0x410UL))
 
 /* Baud-Rate Generator Configuration Registers */
-#define BRG_BRGC(n)            ((volatile uint32_t*)(QE_ENGINE_BASE + 0xC0000 + 0x640UL + ((n-1) * 0x4)))
+#define BRG_BRGC(n)            ((volatile uint32_t*)(QE_BASE + 0xC0000 + 0x640UL + ((n-1) * 0x4)))
 
-#define QE_CP                  (QE_ENGINE_BASE + 0x100UL)  /* Configuration register */
+#define QE_CP                  (QE_BASE + 0x100UL)  /* Configuration register */
 #define QE_CP_CECR             ((volatile uint32_t*)(QE_CP + 0x00)) /* command register */
 #define QE_CP_CECDR            ((volatile uint32_t*)(QE_CP + 0x08)) /* data register */
 #define QE_CP_CERCR            ((volatile uint16_t*)(QE_CP + 0x38)) /* RAM control register */
 
-#define QE_SDMA                (QE_ENGINE_BASE + 0x4000UL) /* Serial DMA */
+#define QE_SDMA                (QE_BASE + 0x4000UL) /* Serial DMA */
 #define QE_SDMA_SDSR           ((volatile uint32_t*)(QE_SDMA + 0x00))
 #define QE_SDMA_SDMR           ((volatile uint32_t*)(QE_SDMA + 0x04))
 #define QE_SDMA_SDAQR          ((volatile uint32_t*)(QE_SDMA + 0x38))
 #define QE_SDMA_SDAQMR         ((volatile uint32_t*)(QE_SDMA + 0x3C))
 #define QE_SDMA_SDEBCR         ((volatile uint32_t*)(QE_SDMA + 0x44))
 
-#define QE_RSP                 (QE_ENGINE_BASE + 0x4100UL) /* Special Registers */
+#define QE_RSP                 (QE_BASE + 0x4100UL) /* Special Registers */
 #define QE_RSP_TIBCR(n, i)     ((volatile uint32_t*)(QE_RSP + ((n) * 0x100) + (i)))
 #define QE_RSP_ECCR(n)         ((volatile uint32_t*)(QE_RSP + ((n) * 0x100) + 0xF0))
 
-#define QE_MURAM               (QE_ENGINE_BASE + 0x110000UL) /* 24KB */
+#define QE_MURAM               (QE_BASE + 0x110000UL) /* 24KB */
 
 #define QE_IRAM_IADD_AIE       0x80000000 /* Auto Increment Enable */
 #define QE_IRAM_IADD_BADDR     0x00080000 /* Base Address */
@@ -1552,6 +1551,9 @@ static int hal_qe_init(void)
     /* Set baud rate configuration */
     set32(BRG_BRGC(1), 0);
 
+    /* Disable all QUICC Engine interrupts */
+    set32(QEIC_CIMR, 0);
+
     return ret;
 }
 #endif /* ENABLE_QUICC */