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rp2350: Define and implement a cpucluster of Cortex-M33s
Assume that users want to run a dual Cortex-M33 on the Pico 2, and update various parts of the codebase to match. I expect the majority of the soc's definition will move from `dts/arm/raspberrypi` to `dts/common/raspberrypi` if/when support is added for the Hazard3 cores. Some parts of the codebase can cope without encoding the cluster in the filename (e.g. Twister's seems to use the identifier in `boards/raspberrypi/rpi_pico2/rpi_pico2.yaml` rather than the filename itself), others can't (e.g. `rpi_pico2_m33_defconfig`) which itself is a form of <board>_<cpucluster>_defconfig and doesn't refer to the SoC. Update documentation to try to highlight the capabilities and limitations of the current support within Zephyr for the Pico 2 board and the underlying SoC. Limited tested locally with no issues found. Signed-off-by: Andrew Featherstone <[email protected]>
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,22 @@ | ||
/* | ||
* Copyright (c) 2024 Andrew Featherstone | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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/dts-v1/; | ||
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/* The build system assumes that there's a cpucluster-specific file. | ||
* | ||
* This file provides composition of the device tree: | ||
* 1. The common features of the SoC | ||
* 2. Core-specific configuration. | ||
* 3. Board-specific configuration. | ||
*/ | ||
#include <raspberrypi/rpi_pico/rp2350a.dtsi> | ||
#include <raspberrypi/rpi_pico/m33.dtsi> | ||
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/* there's nothing specific to the Cortex-M33 cores vs the (not yet | ||
* implemented) Hazard3 cores. | ||
*/ | ||
#include "rpi_pico2.dtsi" |
3 changes: 3 additions & 0 deletions
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...raspberrypi/rpi_pico2/rpi_pico2_defconfig → ...berrypi/rpi_pico2/rpi_pico2_m33_defconfig
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,22 @@ | ||
/* | ||
* Copyright (c) 2024 Andrew Featherstone | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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#include <arm/armv8-m.dtsi> | ||
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/* Model in the device tree a Cortex-M33 core being 'plugged' into each | ||
* 'socket' within the SoC. Within the datasheet these are core 0 and core 1. | ||
*/ | ||
&cpu0 { | ||
compatible = "arm,cortex-m33"; | ||
}; | ||
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&cpu1 { | ||
compatible = "arm,cortex-m33"; | ||
}; | ||
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&nvic { | ||
arm,num-irq-priority-bits = <4>; | ||
}; |
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@@ -7,3 +7,5 @@ family: | |
- name: rp2350 | ||
socs: | ||
- name: rp2350a | ||
cpuclusters: | ||
- name: m33 |
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