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soc: adi: max32: Enable primary core to configure/start secondary core #84539

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merged 2 commits into from
Jan 29, 2025

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MaureenHelm
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Adds support for the primary m4 core to configure the boot address and
start the clock for the secondary risc-v core. Unlike the msdk which
defers this function to applications and requires users to copy/paste
code from an msdk example application into their own application, in
zephyr it is implemented in the common soc init routine of the primary
core. It can be enabled/disabled and configured with Kconfig symbols and
a devicetree chosen node, allowing applications to override board-level
defaults if desired using overlays instead of modifying zephyr code.

Signed-off-by: Maureen Helm [email protected]

Refactors the max32 soc family configuration to allow socs with cores
other than arm cortex-m4. This will make it possible to add support for
the secondary risc-v core that exists on some max32 variants.

Signed-off-by: Maureen Helm <[email protected]>
Adds support for the primary m4 core to configure the boot address and
start the clock for the secondary risc-v core. Unlike the msdk which
defers this function to applications and requires users to copy/paste
code from an msdk example application into their own application, in
zephyr it is implemented in the common soc init routine of the primary
core. It can be enabled/disabled and configured with Kconfig symbols and
a devicetree chosen node, allowing applications to override board-level
defaults if desired using overlays instead of modifying zephyr code.

Signed-off-by: Maureen Helm <[email protected]>
@zephyrbot zephyrbot added the platform: ADI Analog Devices, Inc. label Jan 24, 2025
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It might be useful if you enable risc-v supports for as part of this PR, to full feature has been completed.
Anyway that's fine I assume you are going to send next PR (that enable risc-v support) just after this PR.

@MaureenHelm
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It might be useful if you enable risc-v supports for as part of this PR, to full feature has been completed. Anyway that's fine I assume you are going to send next PR (that enable risc-v support) just after this PR.

The max32 risc-v support I've done so far doesn't support interrupts or the kernel timer, so it's not useful for general purpose yet and I'm a little concerned someone would think they could start running zephyr applications on it. It's currently only useful if someone wants to pick up where I left off and finish the port. If someone is interested, I have zephyr booting the hello world sample to ram console.

I'm upstreaming a subset of that work here to enable a zephyr app on the arm core to start some app (not necessarily a zephyr app) on the risc-v core.

@MaureenHelm
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@ttmut @microbuilder can you take a look?

@MaureenHelm MaureenHelm added this to the v4.1.0 milestone Jan 29, 2025
@kartben kartben merged commit 398d9e3 into zephyrproject-rtos:main Jan 29, 2025
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@MaureenHelm MaureenHelm deleted the max32-riscv-configure branch January 29, 2025 17:19
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5 participants