riscv64: fix incorrect branch target

ziglang · Aug 16, 2024 · 624016e · 624016e
1 parent 9473d76
commit 624016e
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/arch/riscv64/CodeGen.zig b/src/arch/riscv64/CodeGen.zig
@@ -6594,7 +6594,7 @@ fn genInlineMemset(
         .tag = .beq,
         .data = .{
             .b_type = .{
-                .inst = @intCast(func.mir_instructions.len + 4), // points after the last inst
+                .inst = @intCast(func.mir_instructions.len + 3), // points after the last inst
                 .rs1 = count,
                 .rs2 = .zero,
             },