Move feature descriptions out of std.Target.Cpu.Feature

This allows users of std.Target to not include all the description strings in their program if they don't actually use them.

Counting all the bytes of the description strings after they were separated out using this code:

    comptime {
        @setEvalBranchQuota(10000000);
        var total_byte_count: usize = 0;
        for (std.enums.values(Arch)) |arch| {
            const descs = allFeaturesDescList(arch);
            for (descs) |desc| {
                total_byte_count += desc.len;
            }
        }
        @compilelog(total_byte_count);
    }

gives a total size of 146898 bytes or ~143 KiB. However, I have not seen quite that much saved in compiled binaries in practice. A test program like this:

    const std = @import("std");

    pub fn main() !void {
        const target = try std.zig.system.resolveTargetQuery(.{});
        std.debug.print("{any}\n", .{target});
    }

compiled in ReleaseSmall on Windows gives these results:

- Before: 321024 bytes (313.5 KiB)
- After:  219648 bytes (214.5 KiB)
- Delta:  101376 bytes ( 99.0 KiB)

Note: The spirv features were not intended to be changed, but I'm not sure what exact versions of the Headers/Registry were used to generate the current `Target/spirv.zig`. I used commits around the time of the last `Target/spirv.zig` update in May 2021 (98dc8eb); in particular, I used commits 60af2c93c46294a2bc9758889a90d935b6f9325f for SPIRV-Registry and ba29b3f59633836c6bb160b951007c8fc3842dee for SPIRV-Headers. Newer Registry/Headers versions were not used because (1) there are a *lot* more features, more than the current Feature.Set.needed_bit_count and (2) the current update_spirv_features.zig cannot handle some of the new files, e.g. https://raw.githubusercontent.com/KhronosGroup/SPIRV-Registry/main/extensions/EXT/SPV_EXT_relaxed_printf_string_address_space.asciidoc

lib/std/Build.zig

@@ -1383,8 +1383,8 @@ pub fn parseTargetQuery(options: std.Target.Query.ParseOptions) error{ParseFaile
                 diags.unknown_feature_name.?,
                 @tagName(diags.arch.?),
             });
-            for (diags.arch.?.allFeaturesList()) |feature| {
-                std.debug.print(" {s}: {s}\n", .{ feature.name, feature.description });
+            for (diags.arch.?.allFeaturesList(), diags.arch.?.allFeaturesDescList()) |feature, desc| {
+                std.debug.print(" {s}: {s}\n", .{ feature.name, desc });
             }
             return error.ParseFailed;
         },

lib/std/Target.zig

@@ -847,9 +847,6 @@ pub const Cpu = struct {
         /// otherwise null.
         llvm_name: ?[:0]const u8,
 
-        /// Human-friendly UTF-8 text.
-        description: []const u8,
-
         /// Sparse `Set` of features this depends on.
         dependencies: Set,
 
@@ -1407,6 +1404,40 @@ pub const Cpu = struct {
             };
         }
 
+        /// Human-friendly UTF-8 description text for all CPU features Zig is aware of.
+        /// Indexes correspond 1:1 with the return of `allFeaturesList`.
+        ///
+        /// TODO: Move these descriptions strings back into `Cpu.Feature`.
+        ///       See https://github.com/ziglang/zig/issues/21010
+        pub fn allFeaturesDescList(arch: Arch) []const []const u8 {
+            return switch (arch) {
+                .arm, .armeb, .thumb, .thumbeb => &arm.feature_descs,
+                .aarch64, .aarch64_be => &aarch64.feature_descs,
+                .arc => &arc.feature_descs,
+                .avr => &avr.feature_descs,
+                .bpfel, .bpfeb => &bpf.feature_descs,
+                .csky => &csky.feature_descs,
+                .hexagon => &hexagon.feature_descs,
+                .loongarch32, .loongarch64 => &loongarch.feature_descs,
+                .m68k => &m68k.feature_descs,
+                .mips, .mipsel, .mips64, .mips64el => &mips.feature_descs,
+                .msp430 => &msp430.feature_descs,
+                .powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.feature_descs,
+                .amdgcn => &amdgpu.feature_descs,
+                .riscv32, .riscv64 => &riscv.feature_descs,
+                .sparc, .sparc64 => &sparc.feature_descs,
+                .spirv32, .spirv64 => &spirv.feature_descs,
+                .s390x => &s390x.feature_descs,
+                .x86, .x86_64 => &x86.feature_descs,
+                .xtensa => &xtensa.feature_descs,
+                .nvptx, .nvptx64 => &nvptx.feature_descs,
+                .ve => &ve.feature_descs,
+                .wasm32, .wasm64 => &wasm.feature_descs,
+
+                else => &.{},
+            };
+        }
+
         /// All processors Zig is aware of, sorted lexicographically by name.
         pub fn allCpuModels(arch: Arch) []const *const Cpu.Model {
             return switch (arch) {