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riscv: vectors part 3
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@Rexicon226
Rexicon226 committed Jul 5, 2024
1 parent c7473ed commit 775a291
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Showing 10 changed files with 191 additions and 148 deletions.
21 changes: 20 additions & 1 deletion lib/std/start.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -221,7 +221,26 @@ fn riscv_start() callconv(.C) noreturn {
}
break :ret root.main();
},
else => @compileError("expected return type of main to be 'void', 'noreturn', 'u8'"),
.ErrorUnion => ret: {
const result = root.main() catch {
const stderr = std.io.getStdErr().writer();
stderr.writeAll("failed with error\n") catch {
@panic("failed to print when main returned error");
};
break :ret 1;
};
switch (@typeInfo(@TypeOf(result))) {
.Void => break :ret 0,
.Int => |info| {
if (info.bits != 8 or info.signedness == .signed) {
@compileError(bad_main_ret);
}
return result;
},
else => @compileError(bad_main_ret),
}
},
else => @compileError(bad_main_ret),
});
}

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245 changes: 129 additions & 116 deletions src/arch/riscv64/CodeGen.zig
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10 changes: 10 additions & 0 deletions src/arch/riscv64/Encoding.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -285,6 +285,9 @@ pub const Mnemonic = enum {
vaddvv,
vsubvv,

vfaddvv,
vfsubvv,

vadcvv,

vmvvx,
Expand Down Expand Up @@ -316,6 +319,8 @@ pub const Mnemonic = enum {
amomaxud,
amominud,

// TODO: Q extension

pub fn encoding(mnem: Mnemonic) Enc {
return switch (mnem) {
// zig fmt: off
Expand Down Expand Up @@ -542,6 +547,9 @@ pub const Mnemonic = enum {
.vaddvv => .{ .opcode = .OP_V, .data = .{ .vecmath = .{ .vm = true, .funct6 = 0b000000, .funct3 = .OPIVV } } },
.vsubvv => .{ .opcode = .OP_V, .data = .{ .vecmath = .{ .vm = true, .funct6 = 0b000010, .funct3 = .OPIVV } } },

.vfaddvv => .{ .opcode = .OP_V, .data = .{ .vecmath = .{ .vm = true, .funct6 = 0b000000, .funct3 = .OPFVV } } },
.vfsubvv => .{ .opcode = .OP_V, .data = .{ .vecmath = .{ .vm = true, .funct6 = 0b000010, .funct3 = .OPFVV } } },

.vadcvv => .{ .opcode = .OP_V, .data = .{ .vecmath = .{ .vm = true, .funct6 = 0b010000, .funct3 = .OPMVV } } },
.vmvvx => .{ .opcode = .OP_V, .data = .{ .vecmath = .{ .vm = true, .funct6 = 0b010111, .funct3 = .OPIVX } } },

Expand Down Expand Up @@ -702,6 +710,8 @@ pub const InstEnc = enum {

.vaddvv,
.vsubvv,
.vfaddvv,
.vfsubvv,
.vadcvv,
.vmvvx,
.vslidedownvx,
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5 changes: 2 additions & 3 deletions src/arch/riscv64/Mir.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -142,12 +142,11 @@ pub const Inst = struct {
vsetivli,
vsetvl,
vaddvv,
vfaddvv,
vsubvv,
vfsubvv,
vslidedownvx,

// A Extension Instructions
amo,

/// A pseudo-instruction. Used for anything that isn't 1:1 with an
/// assembly instruction.
pseudo,
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4 changes: 2 additions & 2 deletions src/arch/riscv64/bits.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ pub const Memory = struct {
2...2 => .hword,
3...4 => .word,
5...8 => .dword,
else => unreachable,
else => std.debug.panic("fromByteSize {}", .{size}),
};
}

Expand Down Expand Up @@ -221,7 +221,7 @@ pub const Register = enum(u8) {
// zig fmt: off
@intFromEnum(Register.zero) ... @intFromEnum(Register.x31) => 64,
@intFromEnum(Register.ft0) ... @intFromEnum(Register.f31) => if (Target.riscv.featureSetHas(features, .d)) 64 else 32,
@intFromEnum(Register.v0) ... @intFromEnum(Register.v31) => 1024, // TODO: look at suggestVectorSize
@intFromEnum(Register.v0) ... @intFromEnum(Register.v31) => 256, // TODO: look at suggestVectorSize
else => unreachable,
// zig fmt: on
};
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1 change: 0 additions & 1 deletion test/behavior/byteswap.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -100,7 +100,6 @@ test "@byteSwap vectors u8" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;

try comptime vector8();
try vector8();
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1 change: 0 additions & 1 deletion test/behavior/cast.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -1985,7 +1985,6 @@ test "peer type resolution: vector and array and tuple" {
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;

var vec: @Vector(2, i8) = .{ 10, 20 };
var arr: [2]i8 = .{ 30, 40 };
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1 change: 0 additions & 1 deletion test/behavior/globals.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,6 @@ test "store to global vector" {
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;

try expect(vpos[1] == 0.0);
vpos = @Vector(2, f32){ 0.0, 1.0 };
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2 changes: 0 additions & 2 deletions test/behavior/sizeof_and_typeof.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,6 @@ test "@sizeOf on compile-time types" {
}

test "@TypeOf() with multiple arguments" {
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;

{
var var_1: u32 = undefined;
var var_2: u8 = undefined;
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49 changes: 28 additions & 21 deletions test/behavior/vector.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -97,29 +97,41 @@ test "vector int operators" {

test "vector float operators" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_c and comptime builtin.cpu.arch.isArmOrThumb()) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;

inline for ([_]type{ f16, f32, f64, f80, f128 }) |T| {
const S = struct {
fn doTheTest() !void {
var v: @Vector(4, T) = [4]T{ 10, 20, 30, 40 };
var x: @Vector(4, T) = [4]T{ 1, 2, 3, 4 };
_ = .{ &v, &x };
try expect(mem.eql(T, &@as([4]T, v + x), &[4]T{ 11, 22, 33, 44 }));
try expect(mem.eql(T, &@as([4]T, v - x), &[4]T{ 9, 18, 27, 36 }));
try expect(mem.eql(T, &@as([4]T, v * x), &[4]T{ 10, 40, 90, 160 }));
try expect(mem.eql(T, &@as([4]T, -x), &[4]T{ -1, -2, -3, -4 }));
}
};
try S.doTheTest();
try comptime S.doTheTest();
}
const S = struct {
fn doTheTest(T: type) !void {
var v: @Vector(4, T) = .{ 10, 20, 30, 40 };
var x: @Vector(4, T) = .{ 1, 2, 3, 4 };
_ = .{ &v, &x };
try expectEqual(v + x, .{ 11, 22, 33, 44 });
try expectEqual(v - x, .{ 9, 18, 27, 36 });
try expectEqual(v * x, .{ 10, 40, 90, 160 });
try expectEqual(-x, .{ -1, -2, -3, -4 });
}
};

try S.doTheTest(f32);
try comptime S.doTheTest(f32);

try S.doTheTest(f64);
try comptime S.doTheTest(f64);

try S.doTheTest(f16);
try comptime S.doTheTest(f16);

if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO

try S.doTheTest(f80);
try comptime S.doTheTest(f80);

try S.doTheTest(f128);
try comptime S.doTheTest(f128);
}

test "vector bit operators" {
Expand Down Expand Up @@ -1228,7 +1240,6 @@ test "loading the second vector from a slice of vectors" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;

@setRuntimeSafety(false);
var small_bases = [2]@Vector(2, u8){
Expand All @@ -1245,7 +1256,6 @@ test "array of vectors is copied" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;

const Vec3 = @Vector(3, i32);
var points = [_]Vec3{
Expand Down Expand Up @@ -1316,7 +1326,6 @@ test "zero multiplicand" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;

const zeros = @Vector(2, u32){ 0.0, 0.0 };
var ones = @Vector(2, u32){ 1.0, 1.0 };
Expand Down Expand Up @@ -1411,7 +1420,6 @@ test "store to vector in slice" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf and builtin.target.ofmt != .macho) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;

var v = [_]@Vector(3, f32){
.{ 1, 1, 1 },
Expand Down Expand Up @@ -1478,7 +1486,6 @@ test "store vector with memset" {
test "addition of vectors represented as strings" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;

const V = @Vector(3, u8);
const foo: V = "foo".*;
Expand Down

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