more RISC-V backend progress #20474

Rexicon226 · 2024-07-02T11:03:49Z

added @atomicLoad, @atomicStore, @atomicRmw, @fence
made std.simd.suggestVectorLength more accurate for RISC-V
implements boiler-plate for RISC-V vectors

1297 passed, 639 failed - 66.99% passing

Now we generate debug undefined constants when the user asks for them to dedup across the function decl. This takes 2 instructions instead of 7 in the RISC-V backend. TODO, we need to dedupe across function decl boundaries.

* the file's doc-comment was misleading and did not focus on the correct aspect of SIMD * added cpu flag awareness to `suggestVectorLengthForCpu` in order to provide a more accurate vector length

Rexicon226 force-pushed the riscv branch 3 times, most recently from a5d634a to d2a65f9 Compare July 5, 2024 21:25

Rexicon226 force-pushed the riscv branch from d2a65f9 to 527f69b Compare July 10, 2024 05:44

Rexicon226 added 11 commits July 14, 2024 23:02

riscv: @atomicLoad and @atomicStore

ea084e9

riscv: @atomicRmw

0460572

Now we generate debug undefined constants when the user asks for them to dedup across the function decl. This takes 2 instructions instead of 7 in the RISC-V backend. TODO, we need to dedupe across function decl boundaries.

riscv implement @sqrt for f32/f64

27ceb4a

riscv: truncate airStructFieldVal result

7a02878

riscv: implement @fence

3e73f37

simd: correct suggestVectorLength

f2301ba

* the file's doc-comment was misleading and did not focus on the correct aspect of SIMD * added cpu flag awareness to `suggestVectorLengthForCpu` in order to provide a more accurate vector length

riscv: vectors part 1

571aa69

riscv: vectors part 2

09e9812

riscv: vectors part 3

5a2c547

riscv: refactor bin_file and zcu usage

5ec926c

riscv: disable failing tests

5a4fe39

Rexicon226 force-pushed the riscv branch from 3040c18 to 5a4fe39 Compare July 15, 2024 06:04

kubkon merged commit 9d9b5a1 into ziglang:master Jul 17, 2024
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more RISC-V backend progress #20474

more RISC-V backend progress #20474

Rexicon226 commented Jul 2, 2024 •

edited

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more RISC-V backend progress #20474

more RISC-V backend progress #20474

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Rexicon226 commented Jul 2, 2024 • edited Loading

Rexicon226 commented Jul 2, 2024 •

edited

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