V0.6

What's Changed

• started DE10 board support development by @AndreMerendeira in #113
• updated gitignore to ignore synthesis files in DE10 and ku040 boards by @AndreMerendeira in #114
• minor improvement (clean target) by @JDLopes in #115
• update CACHE submodule by @JDLopes in #117
• improve Makefiles by @JDLopes in #120
• revert console Makefile by @JDLopes in #124
• Fixed DE10-Lite frequency and baud-rate. Added missing BOARD_USER. Fixed DE10-Lite top_system.tcl by @AndreMerendeira in #125
• update UART submodule by @JDLopes in #128
• Added xilinx reports generation by @pedrompt97 in #129
• update ASIC framework to use new Makefiles; change FIRM_ADDR_W and SRAM_ADDR_W default values; fix bug by @JDLopes in #130
• Makefile revamp working for DE10 FPGA by @P-Miranda in #132
• improve asic Makefile; update UART submodule by @JDLopes in #133
• fixed DE10 support (IS_CYCLONE was 1) by @AndreMerendeira in #134
• Makefile revamp by @AndreMerendeira in #135
• fix Makefile clean targets; add missing target to .PHONY list in simulation.mk Makefile segment by @JDLopes in #137
• improve xcelium Makefile by @JDLopes in #138
• improve documentation Makefiles by @JDLopes in #139
• Added git password cache to README by @P-Miranda in #140
• update presentation: update example firmware code and its output by @JDLopes in #141
• add a slide with the run on FPGA output by @JDLopes in #142
• fix Makefiles clean target; add missing command for transferring FPGA log files to the local machine; fix pb document generation; minor corrections to the README.md file; update UART submodule by @JDLopes in #143
• implement lock files when using FPGAs; update test.expected file for xcelium simulator by @JDLopes in #144
• update UART submodule by @JDLopes in #145
• improve lock and unlock targets by @JDLopes in #147
• kill remote tools when Ctrl+C is typed in by @JDLopes in #148
• fix unlock fpga, when Makefiles are run from BOARD_SERVER by @JDLopes in #149
• fix run target for FPGAs by @JDLopes in #150
• implement queue for using FPGAs; add variables for manage FPGA loads by @JDLopes in #152
• changed soffice to libreoffice by @AndreMerendeira in #151
• switch append file for overwrite file by @JDLopes in #154
• fix Vivado path by @JDLopes in #156
• updated submodule UART by @DiogoFausto in #157
• fix misspelled command by @JDLopes in #158
• remove lock files for FPGAs; change FPGA log file content; fix board path by @JDLopes in #161
• uncomment create_clock in xdc file; add missing dependencies to system.v and system_tb.v targets by @JDLopes in #175
• update UART submodule; use _be memories in sram module; update CACHE submodule; update hardware.mk; update test.expected files for simulators and FPGAs; merge with branch master by @JDLopes in #177
• fix presentation Makefile: add missing variables by @JDLopes in #178
• Asic by @microSharjeel in #182
• fix Makefile: add missing variable definitions; update UART submodule by @JDLopes in #183
• add framework to generate ASIC memories; update .gitignore file by @JDLopes in #190
• Readme for OpenLane by @microSharjeel in #193
• update .expected files; use --delete flag on clean-remote targets only; fix .gitignore file; minor improvements in FPGAs' Makefiles; merge with iob-soc/master by @JDLopes in #199
• update CACHE submodule; update sources according to the new CACHE submodule; remove asic-mems target from root Makefile; fix DDR_ADDR_W define in asic.mk by @JDLopes in #200
• define MEM_DIR in system.mk; update paths in hardware.mk; add targets to generate memories' wrappers; update CACHE submodule by @JDLopes in #202
• fix targets for memory wrappers; change shell script permissions; fix sram.v generation for ASIC; improve asic.mk; cleanup datasheet files from ASIC memories; transfer ASIC reports from server to local machine; use CASE variable to filter libraries to use on synthesis for ASIC; update CACHE submodule; update sources according new submodule; rename XMSIM_SERVER and XMSIM_USER variables to CADENCE_SERVER and CADENCE_USER by @JDLopes in #203
• move test.log for FPGAs from console to FPGA directory; remove dummy character by @JDLopes in #204
• fix clean-testlog target by @JDLopes in #205
• Python3 by @P-Miranda in #207
• major ASIC Makefiles revamp; change initial.v file name to initial_sram.v; update .gitignore file; update root Makefile; update simulation.mk; update CACHE and UART submodules by @JDLopes in #206
• add missing axi signals for full AXI4-full protocol support; merge with iob-soc/master by @JDLopes in #209
• fix .queue and .load files' permissions by @JDLopes in #212
• Axi4 signals missingmerge with iob-soc/master by @JDLopes in #213
• README for OpenLane and OpenRAM by @microSharjeel in #221
• update CACHE submodule; update sources according to new CACHE by @JDLopes in #222
• Include submodules based on corename instead of submodule folder name by @arturum1 in #210
• fix ASIC RAM initialization; update CACHE submodule; merge with iob-soc/master by @JDLopes in #223
• fix merge with iob-soc/master by @JDLopes in #224
• Asic by @microSharjeel in #225
• fix ASIC tests' targets; change ASIC framework for synthesize iob-soc with DDR access; fix ASIC memories' targets; update UART and CACHE submodules by @JDLopes in #226
• update test.expected file for xcelium simulator by @JDLopes in #227
• Makefile for OpenRAM/OpenLane. OpenRAM make rule added by @microSharjeel in #228
• Create myconfig.py by @microSharjeel in #230
• Asic by @microSharjeel in #231
• Asic by @microSharjeel in #232
• make ASIC simulation memories' files depend on technology node; add ifdef SRAM_INIT in initial_dp_ram.v file to avoid simulation warnings; move hex_split and makehex scripts from iob-soc to iob-mem; remove unused python scripts; update CACHE submodule; update source files; merge with iob-soc/master by @JDLopes in #237
• Addresses #146 by @P-Miranda in #238
• Changes in Makefile for OpenLane Docker start by @microSharjeel in #239
• update CPU submodule; update sources by @JDLopes in #240
• rename SUBMODULES_TMP to SUBMODULES by @JDLopes in #242
• Console/TB waits for ACK before sending file by @AndreMerendeira in #243
• updated UART by @AndreMerendeira in #244
• minor changes in hardware.mk; update CACHE, LIB, MEM, TEX and UART submodules by @JDLopes in #246
• update CACHE, CPU and INTERCON submodules by @JDLopes in #247
• update CACHE and UART submodules by @JDLopes in #248
• Added target for openlane flow by @microSharjeel in #245
• temp folder and copy target for testing by @microSharjeel in #250
• add ASIC variable for generate documents; include asic_results.tex file if ASIC=1; remove TEX and INTERCON submodules; update UART submodule by @JDLopes in #251
• Changes made for OpenLane and now it is working by @microSharjeel in #252
• update pb.expected file; add presentation.expected file to NO_CLEAN list; cleanup presentation folder; update UART submodule by @JDLopes in #253
• remove unnecessary if statement from hardware.mk; add corename target; update all submodules by @JDLopes in #254
• update CACHE and MEM submodules by @JDLopes in #255
• Made changes in README.md according to comments by @microSharjeel in #256
• add MODULE to MODULES list softcoded; update all submodules by @JDLopes in #257
• remove MODULE variable; update all submodules by @JDLopes in #258
• merge with branches ack_after_filesz and asic from iob-soc by @JDLopes in #259
• update .expected files by @JDLopes in #260
• merge with iob-soc/corename by @JDLopes in #261
• update .sh scripts; update UART submodule by @JDLopes in #262
• update CACHE and UART submodules by @JDLopes in #265
• update CACHE and MEM submodules by @JDLopes in #266
• update UART submodule by @JDLopes in #267
• update CACHE and UART submodules by @JDLopes in #268
• add if statement to prevent error when TEST_LOG file is not set by @JDLopes in #271
• Fixed a typo in figures and presentation. make test-doc now uses resources with DDR=0 by @AndreMerendeira in #272
• added fpga-build-all and fpga-clean-all by @AndreMerendeira in #273
• update CACHE, LIB, MEM and UART submodules by @JDLopes in #281

New Contributors

• @DiogoFausto made their first contribution in #157

Full Changelog: V0.5...V0.6