tmp commit #2
Annotations
10 errors and 11 warnings
lint-license:
scripts/openocd/vcu128-2-digilent.cfg#L1
FAILED: File does not start with comment
|
lint-license:
scripts/openocd/vcu128-2-digilent.cfg#L1
FAILED: File does not start with comment
|
lint-license:
sw/tests/rvv_test.h#L1
FAILED: File does not start with comment
|
lint-license:
target/common/ara.mk#L6
FAILED: First comment ended before licence notice
|
lint-license:
target/sim/vsim/mmu_stub_run.tcl#L1
FAILED: File does not start with comment
|
lint-license:
target/sim/vsim/vsim.mk#L1
FAILED: File does not start with comment
|
lint-license:
target/xilinx/scripts/tcl/get_run_info.tcl#L1
FAILED: File does not start with comment
|
lint-license
Process completed with exit code 1.
|
lint-sv
reviewdog: Too many results (annotations) in diff.
You may miss some annotations due to GitHub limitation for annotation created by logging command.
Please check GitHub Actions log console to see all results.
Limitation:
- 10 warning annotations and 10 error annotations per step
- 50 annotations per job (sum of annotations from all the steps)
- 50 annotations per run (separate from the job annotations, these annotations aren't created by users)
Source: https://github.community/t5/GitHub-Actions/Maximum-number-of-annotations-that-can-be-created-using-GitHub/m-p/39085
|
lint-sv
Process completed with exit code 1.
|
lint-license
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/setup-python@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
|
lint-sv:
hw/mmu_stub.sv#L13
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 135 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 135 [Style: line-length] [line-length]" location:{path:"hw/mmu_stub.sv" range:{start:{line:13 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
|
lint-sv:
hw/mmu_stub.sv#L77
[verible-verilog-lint] reported by reviewdog 🐶
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw Output:
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/mmu_stub.sv" range:{start:{line:77 column:41}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:77 column:41} end:{line:78}} text:" // NOTE: Assumes Ara consumes it\n"}
|
lint-sv:
hw/mmu_stub.sv#L89
[verible-verilog-lint] reported by reviewdog 🐶
File must end with a newline. [Style: posix-file-endings] [posix-eof]
Raw Output:
message:"File must end with a newline. [Style: posix-file-endings] [posix-eof]" location:{path:"hw/mmu_stub.sv" range:{start:{line:89 column:21}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:89 column:21} end:{line:90}} text:"endmodule : mmu_stub\n"}
|
lint-sv:
hw/cheshire_soc.sv#L595
[verible-verilog-lint] reported by reviewdog 🐶
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw Output:
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:595 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:595 column:1} end:{line:597}} text:"\n // CSR\n"}
|
lint-sv:
hw/cheshire_soc.sv#L596
[verible-verilog-lint] reported by reviewdog 🐶
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw Output:
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:596 column:11}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
|
lint-sv:
hw/cheshire_soc.sv#L669
[verible-verilog-lint] reported by reviewdog 🐶
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw Output:
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:669 column:28}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:669 column:28} end:{line:670}} text:"`ifdef ARA_INTEGRATION_V0_2\n"}
|
lint-sv:
hw/cheshire_soc.sv#L681
[verible-verilog-lint] reported by reviewdog 🐶
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw Output:
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:681 column:7}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:681 column:7} end:{line:682}} text:" //\n"}
|
lint-sv:
hw/cheshire_soc.sv#L689
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:689 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
|
lint-sv:
hw/cheshire_soc.sv#L738
[verible-verilog-lint] reported by reviewdog 🐶
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw Output:
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:738 column:63}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:738 column:63} end:{line:746}} text:" .en_ld_st_translation_i ( xvio_en_ld_st_translation_i ),\n .trigger_exception_i ( xvio_mmu_exception_i ),\n .misaligned_ex_i ( mmu_misaligned_ex_acc_cva6 ),\n .is_store_i ( mmu_is_store_acc_cva6 ),\n .dtlb_ppn_o ( mmu_dtlb_ppn_cva6_acc ),\n .paddr_o ( mmu_paddr_cva6_acc ),\n .exception_o ( mmu_exception_cva6_acc )\n`else // !MMU_STUB\n"}
|
lint-sv:
hw/cheshire_soc.sv#L739
[verible-verilog-lint] reported by reviewdog 🐶
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw Output:
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:739 column:63}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
|