Some minor fixes.

MiSTer-devel · Mar 23, 2023 · 53fee7f · 53fee7f
1 parent 8947c8a
commit 53fee7f
Show file tree

Hide file tree

Showing 6 changed files with 56 additions and 72 deletions.
diff --git a/Arcade-DonkeyKong.qsf b/Arcade-DonkeyKong.qsf
@@ -13,10 +13,11 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
-set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Standard Edition"
 
 set_global_assignment -name GENERATE_RBF_FILE ON
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name SAVE_DISK_SPACE OFF
 set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
@@ -46,7 +47,7 @@ set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
 set_global_assignment -name ECO_OPTIMIZE_TIMING ON
 set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
 set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
-set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
 set_global_assignment -name SEED 1
 
 set_global_assignment -name VERILOG_MACRO "MISTER_FB=1"
@@ -63,36 +64,4 @@ source sys/sys.tcl
 source sys/sys_analog.tcl
 source files.qip
 set_global_assignment -name FLOW_ENABLE_RTL_VIEWER OFF
-set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/Log2highacc.sv"
-set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/natural_log.sv"
-set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/LFSR.sv"
-set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/resistive_two_way_mixer.sv"
-set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/astable_555_vco.sv"
-set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/resistor_capacitor_low_pass_filter.sv"
-set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/resistor_capacitor_high_pass_filter.sv"
-set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/rate_of_change_limiter.sv"
-set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/invertor_square_wave_oscilator.sv"
-set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/dk_walk.sv"
-set_global_assignment -name CDF_FILE jtag.cdf
-set_global_assignment -name QIP_FILE sys/sys.qip
-set_global_assignment -name VERILOG_FILE rtl/dkong_top.v
-set_global_assignment -name VERILOG_FILE rtl/dkong_dma.v
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VERILOG_FILE rtl/i8035ip.v
-set_global_assignment -name VERILOG_FILE rtl/dkong_wav_sound.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/dkong_soundboard.sv
-set_global_assignment -name VERILOG_FILE rtl/dkong_vram.v
-set_global_assignment -name VERILOG_FILE rtl/dkong_sound.v
-set_global_assignment -name VERILOG_FILE rtl/dkong_obj.v
-set_global_assignment -name VERILOG_FILE rtl/dkong_logic.v
-set_global_assignment -name VERILOG_FILE rtl/dkong_hv_count.v
-set_global_assignment -name VERILOG_FILE rtl/dkong_col_pal.v
-set_global_assignment -name VERILOG_FILE rtl/dkong_bram.v
-set_global_assignment -name VERILOG_FILE rtl/dkong_adec.v
-set_global_assignment -name VERILOG_FILE rtl/radarscp_stars.v
-set_global_assignment -name QIP_FILE rtl/t48/T48.qip
-set_global_assignment -name QIP_FILE rtl/T80/T80.qip
-set_global_assignment -name VERILOG_FILE rtl/pause.v
-set_global_assignment -name VERILOG_FILE rtl/hiscore.v
-set_global_assignment -name SYSTEMVERILOG_FILE "Arcade-DonkeyKong.sv"
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/Arcade-DonkeyKong.sv b/Arcade-DonkeyKong.sv
@@ -284,7 +284,7 @@ reg [7:0] sw[8];
 always @(posedge clk_sys) if (ioctl_wr && (ioctl_index==254) && !ioctl_addr[24:3]) sw[ioctl_addr[2:0]] <= ioctl_dout;
 
 // Core specific mods
-reg mod_dk = 0;
+//reg mod_dk = 0;
 reg mod_dkjr = 0;
 reg mod_dk3 = 0;
 reg mod_radarscope=0;
@@ -295,7 +295,7 @@ always @(posedge clk_sys) begin
 	reg [7:0] mod = 0;
 	if (ioctl_wr & (ioctl_index==1)) mod <= ioctl_dout;
 
-	mod_dk <= (mod == 0);
+	//mod_dk <= (mod == 0);
 	mod_dkjr <= (mod == 1);
 	mod_dk3 <= (mod == 2);
 	mod_radarscope <= (mod == 3);
@@ -339,10 +339,10 @@ wire [3:0] r,g,b;
 
 reg ce_pix;
 always @(posedge clk_49) begin
-        reg [2:0] div;
+	reg [2:0] div;
 
-        div <= div + 1'd1;
-        ce_pix <= !div;
+	div <= div + 1'd1;
+	ce_pix <= !div;
 end
 
 wire no_rotate = status[2] | direct_video | mod_pestplace;
@@ -375,24 +375,23 @@ assign AUDIO_S = 1;
 
 assign hblank = hbl[8];
 
-reg  ce_vid;
+//reg  ce_vid;
 wire clk_pix;
 wire hbl0;
 reg [8:0] hbl;
 always @(posedge clk_sys) begin
 	reg old_pix;
 	old_pix <= clk_pix;
-	ce_vid <= 0;
+	//ce_vid <= 0;
 	if(~old_pix & clk_pix) begin
-		ce_vid <= 1;
+		//ce_vid <= 1;
 		hbl <= (hbl<<1)|hbl0;
 	end
 end
 
 wire reset = RESET | status[0] | buttons[1]| ioctl_download;
 
 
-
 wire [15:0] main_rom_a;
 wire [7:0] main_rom_do;
 wire [11:0] sub_rom_a;

diff --git a/files.qip b/files.qip
@@ -14,6 +14,16 @@ set_global_assignment -name VERILOG_FILE rtl/dkong_bram.v
 set_global_assignment -name VERILOG_FILE rtl/dkong_adec.v
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/dkongjr_dac.sv
 set_global_assignment -name VERILOG_FILE rtl/dkongjr_iir_filter.v
+set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/Log2highacc.sv"
+set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/natural_log.sv"
+set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/LFSR.sv"
+set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/resistive_two_way_mixer.sv"
+set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/astable_555_vco.sv"
+set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/resistor_capacitor_low_pass_filter.sv"
+set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/resistor_capacitor_high_pass_filter.sv"
+set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/rate_of_change_limiter.sv"
+set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/invertor_square_wave_oscilator.sv"
+set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mister-discrete/dk_walk.sv"
 set_global_assignment -name VERILOG_FILE rtl/radarscp_stars.v
 set_global_assignment -name QIP_FILE rtl/t48/T48.qip
 set_global_assignment -name QIP_FILE rtl/T80/T80.qip

diff --git a/rtl/dkong_wav_sound.v b/rtl/dkong_wav_sound.v
@@ -30,16 +30,16 @@ module dkong_wav_sound #(
 localparam WAV_SAMPLE_RATE = 11025; // Hz
 localparam Sample_cnt = CLOCK_RATE / WAV_SAMPLE_RATE;
 
-parameter Wlk1_adr = 16'h0000; // 10000 - 107FF
-parameter Wlk1_cnt = 16'h07d0; // 10000 - 107CF
-parameter Wlk2_adr = 16'h0800; // 10800 - 10FFF
-parameter Wlk2_cnt = 16'h07d0; // 10800 - 10FCF
-parameter Jump_adr = 16'h1000; // 11000 - 12FFF
-parameter Jump_cnt = 16'h1e20; // 11000 - 12E1F
-parameter Foot_adr = 16'h3000; // 13000 - 14FFF
-parameter Foot_cnt = 16'h1750; // 13000 - 1474F
-parameter Wlk3_adr = 16'h4800; // 14800 - 14FFF
-parameter Wlk3_cnt = 16'h07d0; // 14800 - 14FCF
+localparam Wlk1_adr = 16'h0000; // 10000 - 107FF
+localparam Wlk1_cnt = 16'h07d0; // 10000 - 107CF
+localparam Wlk2_adr = 16'h0800; // 10800 - 10FFF
+localparam Wlk2_cnt = 16'h07d0; // 10800 - 10FCF
+localparam Jump_adr = 16'h1000; // 11000 - 12FFF
+localparam Jump_cnt = 16'h1e20; // 11000 - 12E1F
+localparam Foot_adr = 16'h3000; // 13000 - 14FFF
+localparam Foot_cnt = 16'h1750; // 13000 - 1474F
+localparam Wlk3_adr = 16'h4800; // 14800 - 14FFF
+localparam Wlk3_cnt = 16'h07d0; // 14800 - 14FCF
 // Contrary to comment in header, the Gorilla roar sound is still in the mra file:
 // parameter Roar_adr = 16'h5000; // 15000 - 198FF
 // parameter Roar_cnt = 16'h4900; // 15000 - 198FF

diff --git a/sys/ascal.vhd b/sys/ascal.vhd
@@ -428,7 +428,7 @@ ARCHITECTURE rtl OF ascal IS
 	SIGNAL o_vrr,o_isync,o_isync2 : std_logic;
 	SIGNAL o_vrr_sync,o_vrr_sync2 : boolean;
 	SIGNAL o_vrr_min,o_vrr_min2 : boolean;
-	SIGNAL o_vrr_max,o_vrr_max2 : boolean;
+	SIGNAL o_vrr_max,o_vrr_max2 : boolean;
 	SIGNAL o_vcpt_sync,o_vcpt_sync2, o_vrrmax : uint12;
 	SIGNAL o_sync, o_sync_max : boolean;
 	SIGNAL o_vmin,o_vmax,o_vdisp : uint12;
@@ -2693,17 +2693,17 @@ BEGIN
 					o_pev(2)<='0';
 					o_end(2)<='0';
 				END IF;
-			END IF;
-
+			END IF;
+
 			o_vcpt_sync2<=o_vcpt_sync;
 			o_vrr_min<=(o_vcpt_sync2<o_vtotal);
 			o_vrr_min2<=o_vrr_min;
-			o_vrr_max<=(o_vcpt_sync2<o_vrrmax);
-			o_vrr_max2<=o_vrr_max;
-
+			o_vrr_max<=(o_vcpt_sync2<o_vrrmax);
+			o_vrr_max2<=o_vrr_max;
+
 			IF o_isync2='1' THEN
-				o_vcpt_sync<=0;
-				o_sync_max<=o_vrr_max2;
+				o_vcpt_sync<=0;
+				o_sync_max<=o_vrr_max2;
 				IF o_vrr_min2 THEN
 					o_sync<=true;
 				END iF;

diff --git a/sys/sys_top.v b/sys/sys_top.v
@@ -519,17 +519,6 @@ cyclonev_hps_interface_peripheral_uart uart
 	.txd(uart_txd)
 );
 
-wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso;
-cyclonev_hps_interface_peripheral_spi_master spi
-(
-	.sclk_out(aspi_sck),
-	.txd(aspi_mosi), // mosi
-	.rxd(aspi_miso), // miso
-
-	.ss_0_n(aspi_ss),
-	.ss_in_n(1)
-);
-
 wire [63:0] f2h_irq = {video_sync,HDMI_TX_VS};
 cyclonev_hps_interface_interrupts interrupts
 (
@@ -635,11 +624,13 @@ ddr_svc ddr_svc
 	.ram_write(ram2_write),
 	.ram_bcnt(ram2_bcnt),
 
+`ifndef MISTER_DISABLE_ALSA
 	.ch0_addr(alsa_address),
 	.ch0_burst(1),
 	.ch0_data(alsa_readdata),
 	.ch0_req(alsa_req),
 	.ch0_ready(alsa_ready),
+`endif
 
 	.ch1_addr(pal_addr),
 	.ch1_burst(128),
@@ -1477,8 +1468,10 @@ audio_out audio_out
 	.core_l(audio_l),
 	.core_r(audio_r),
 
+`ifndef MISTER_DISABLE_ALSA
 	.alsa_l(alsa_l),
 	.alsa_r(alsa_r),
+`endif
 
 	.i2s_bclk(HDMI_SCLK),
 	.i2s_lrclk(HDMI_LRCLK),
@@ -1491,6 +1484,18 @@ audio_out audio_out
 );
 
 
+`ifndef MISTER_DISABLE_ALSA
+wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso;
+cyclonev_hps_interface_peripheral_spi_master spi
+(
+	.sclk_out(aspi_sck),
+	.txd(aspi_mosi), // mosi
+	.rxd(aspi_miso), // miso
+
+	.ss_0_n(aspi_ss),
+	.ss_in_n(1)
+);
+
 wire [28:0] alsa_address;
 wire [63:0] alsa_readdata;
 wire        alsa_ready;
@@ -1517,6 +1522,7 @@ alsa alsa
 	.pcm_l(alsa_l),
 	.pcm_r(alsa_r)
 );
+`endif
 
 ////////////////  User I/O (USB 3.0 connector) /////////////////////////