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Known issues
Title: Reference NIC
Type: Bug
Affected Projects/Modules: Reference NIC
Description: DMA hangs after iperf testing with specific tool versions and devices. Details here
Status: No plans for further investigations.
Title: Design Flow
Type: Information
Affected Projects/Modules: Reference projects
Description: Some of the reference projects are currently designed using the block design hierarchies, while others are using verilog based hierarchies (some of these embed block designs as modules, rather than top).
Status: A single design flow is expected to be adopted in the future.
Title: Insufficient HW test indications
Type: Enhancement
Affected Projects/Modules: All projects
Description: The HW test does not provide sufficient indications to understand what went wrong and why, e.g. which packet had an error, type of error etc.
Status: Future enhancement
Title: Unified Synthesis and Simulation Environment
Type: Enhancement
Affected Projects/Modules: Reference NIC/Switch
Description: The reference projects currently have separate environments (top hierarchy, tcl script) for simulation and synthesis. The simulation covers only the datapath and not interfaces.
Status: Future enhancement
Title: Header checking is missing from simulation
Type: Enhancement
Affected Projects/Modules: All projects
Description: The simulation framework announces that a test has passed if the axi expected file matches the axi log file. However, in the generation of the axi expected file, there is (in reference tests) no checking of the headers - e.g. that the length field matches the actual packet length, checksum etc.
Status: No plan to add. This is project specific, and users should update this per project/test according to their headers type.
Title: Syntax check when packaging an IP
Type: Enhancement
Affected Projects/Modules: Packaged IPs
Description: When packaging an IP core, Vivado does not indicate syntax errors. It fails to include an HDL file with syntax errors in the ports and parameters (possibly other errors too), and gives the error:
CRITICAL WARNING: [filemgmt 20-742] The top module "module_name" specified for this project can not be validated. The current project is using automatic hierarchy update mode, and hence a new suitable replacement top will be automatically selected. If this is not desired, please change the hierarchy update mode to one of the manual compile order modes first, and then set top to any desired value. …..
ERROR: [fidma register reading bug for reference_niclemgmt 20-730] Could not find a top module in the fileset sources_1. ……
Status: Future Enhancement
Title: No access to registers using UART in Reference Switch
Type: Enhancement
Affected Projects/Modules: Reference Switch Lite
Description: When using UART, only the microblaze can be accessed but not the modules' registers. This is currently not supported by the design.
Status: Future Enhancement
**Title:**Registers read may continuously fail
Type: Bug
Affected Projects/Modules: Reference Switch, possibly other projects
Description: Registers access may fail for a newly synthesized design (not the released code). This can be triggered by minor changes to the design, such as changing an AXIS FIFO depth. Timing may pass, but access to the registers will fail, returning 0x0000 and then ioctl error.
Status: Open
Title: Reduced Throughput
Type: Open Issue
Affected Projects/Modules: All
Description: Reference projects experience throughput that is less than optimal. For the reference_NIC this is largely caused by DMA. For the switch this is caused by 10G port flow control, and the basic pipeline design.
Status: Future enhancements
Title: Log file for acceptance test
Type: Information
**Affected Projects/Modules:**Acceptance test
Description: When you perform the acceptance test, if you close the testing GUI and reopen it, the file NfSumeTest.log is overwritten with the new tests.
Status: Future enhancement
Title: "Failed" acceptance tests
Type: Information
Affected Projects/Modules: Acceptance test
Description: Some of the tests (especially memory tests) may occasionally appear to fail. Usually this is due to the initialization of the memory calibration signals, not due to the malfunctioning of the components. Try repeating the tests and if tests repeatedly fail, then it might be a component failure. In this case, you should contact the supplier.
Status: Future enhancement
Title: Refreshing the acceptance GUI
Type: Information
Affected Projects/Modules: Acceptance test
Description: Sometimes the results of the acceptance tests are not updated in the result column. This is because of issues relating to object updates in wxpython. This also prevents the refresh button in the GUI from being functional. This is currently being looked into. One way to get around this situation is to close the GUI and reopen it.
Status: Future enhancement
Title: Direct Attach Cables (DAC) & SFP+ Network Cards
Type: Information
Affected Projects/Modules: Reference_switch
Description: Connecting external SFP+ interfaces to FPGA SUME SFP+ interfaces using DAC may have issues. We had an issue of connecting FPGA SUME SFP+ interfaces to Solarflare SFN8522 using SFP-H10GB-CU3M-C cables. The Solarflare's interfaces were DOWN. However, this problem was solved by replacing Solarflare card by Intel 82599ES card.
we also had an issue with 10GTek DAC cables and Solarflare card combination. The SFP+ interfaces were UP but the test was failed because packets were not transmitted.
Cisco SFP-10AOC3M SFP+ Active Optical Cables work with Solarflare card.
Status: Open Issue
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