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Known issues
- Reference NIC only - Occasional packet corruption
It was observed inconsistent lengths between RIFFA and the plan from the the 128b meta-information. The real reason for that was that the 128b meta-information was not actually that, the "magic" 0xcafe wasn't there either. This suggests that it's a flow-control and/ or RIFFA DMA block issue.
- Insufficient HW test indications
The HW test does not provide sufficient indications to understand what went wrong and why, i.e. it indicates number of errors, but not what went wrong and/ or why PCAP files should not be the first line of debug - basic failure information is required before that (e.g. packet number that failed). Registers error information is not sufficient (currently just indicates a register error).
- HW test freezes
HW test freezes indefinitely if expected packets are not received.
- HW test does not dump registers information
Dump registers information during hw test.
- Header checking is missing from simulation
The simulation framework announces that a test has passed if the axi expected file matches the axi log file. However, in the generation of the axi expected file, there is (in reference tests) no checking of the headers - e.g. that the length field matches the actual packet length, checksum etc. These are probably just a matter of calling the right scapy options. This is an enhancement that can help many users, especially those that modify the packet's contents.
- Syntax check when packaging an IP
When packaging an IP core, Vivado does not indicate syntax errors. It fails to include an HDL file with syntax errors in the ports and parameters (possibly other errors too), and gives the error:
CRITICAL WARNING: [filemgmt 20-742] The top module "module_name" specified for this project can not be validated. The current project is using automatic hierarchy update mode, and hence a new suitable replacement top will be automatically selected. If this is not desired, please change the hierarchy update mode to one of the manual compile order modes first, and then set top to any desired value. …..
ERROR: [fidma register reading bug for reference_niclemgmt 20-730] Could not find a top module in the fileset sources_1. ……
- GUI - Running tests
- When running dma register reading bug for reference_nic tests from the gui: if you stop a test once it started, the GUI gets stuck and all you can do is close it and start again. Keep in mind that restarting the GUI will overwrite the log file.
- If you start a new test when a previous run is running, the first one gets interrupted and is not automatically resumed.
- The "remaining time" in tests is not really reliable, it shows weird times. Most tests will take about 30 seconds to complete.
- DMA register reading bug for reference_nic
The symptom shows the following:
- Reading for DMA register only will not return a proper value until several times later.
- Then the hardware stacks, and register reading is not working at all.
e.g. Try to read 0x44080000 which is the ID using rwaxi:
- First time returns 0x0000.
- Second time it returns 0x1ffa.
- Try other address reading, shows random things, sometimes 0x1ffa and sometimes 0x0000.