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Known issues
Title: Design Flow
Type: Information
Affected Projects/Modules: Reference projects
Description: Some of the reference projects are currently designed using the block design hierarchies, while others are using verilog based hierarchies (some of these embed block designs as modules, rather than top).
Status: A single design flow is expected to be adopted in the future.
Title: Reference Router is Missing
Type: Information
Affected Projects/Modules: Reference Router project
Description: The reference router project is not included in this release
Status: Expected to be added in future releases.
Title: Vivado 2014.4
Type: Information
Affected Projects/Modules: All
Description: The first release is using Vivado 2014.4, which is now outdated.
Status: Vivado release is expected to be updated in the future.
Title: Insufficient HW test indications
Type: Enhancement
**Affected Projects/Modules:**All projects
Description: The HW test does not provide sufficient indications to understand what went wrong and why, e.g. which packet had an error, type of error etc.
Status: Future enhancement
Title: Unified Synthesis and Simulation Environment
Type: Enhancement
Affected Projects/Modules: Reference NIC/Switch
Description: The reference projects currently have separate environments (top hierarchy, tcl script) for simulation and synthesis. The simulation covers only the datapath and not interfaces.
Status: Future enhancement
Title: Header checking is missing from simulation
**Type:**Enhancement
**Affected Projects/Modules:**All projects
**Description:**The simulation framework announces that a test has passed if the axi expected file matches the axi log file. However, in the generation of the axi expected file, there is (in reference tests) no checking of the headers - e.g. that the length field matches the actual packet length, checksum etc.
**Status:**No plan to add. This is project specific, and users should update this per project/test according to their headers type.
Title: Syntax check when packaging an IP
Type: Enhancement
Affected Projects/Modules: Packaged IPs
Description: When packaging an IP core, Vivado does not indicate syntax errors. It fails to include an HDL file with syntax errors in the ports and parameters (possibly other errors too), and gives the error:
CRITICAL WARNING: [filemgmt 20-742] The top module "module_name" specified for this project can not be validated. The current project is using automatic hierarchy update mode, and hence a new suitable replacement top will be automatically selected. If this is not desired, please change the hierarchy update mode to one of the manual compile order modes first, and then set top to any desired value. …..
ERROR: [fidma register reading bug for reference_niclemgmt 20-730] Could not find a top module in the fileset sources_1. ……
Status: Future Enhancement
Title: DMA register reading bug for reference_nic
Type: Bug
**Affected Projects/Modules:**Reference NIC
Description: The symptom shows the following:
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Reading for DMA register only will not return a proper value until several times later.
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Then the hardware gets stuck, and register reading is not working at all. e.g. Try to read 0x44080000 which is the ID using rwaxi:
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First time returns 0x0000.
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Second time it returns 0x1ffa.
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Try other address reading, shows random things, sometimes 0x1ffa and sometimes 0x0000.
**Status:**Open
Title: No access to registers using UART in Reference Switch
Type: Enhancement
Affected Projects/Modules: Reference Switch Lite
Description: When using UART, only the microblaze can be accessed but not the modules' registers. This is currently not supported by the design.
Status: Future Enhancement
Title: Reference Switch does not support DMA packets
Type: Enhancement
Affected Projects/Modules: Reference Switch Lite
Description: The reference switch currently uses only 4 ports (nf0-nf3), and the DMA is not used as part of the switch (i.e. to send/receive packets). The DMA is used only for registers access.
Status: Future Enahancement
**Title:**Registers read may continuously fail
Type: Bug
Affected Projects/Modules: Reference Switch, possibly other projects
Description: Registers access may fail for a newly synthesized design (not the released code). This can be triggered by minor changes to the design, such as changing an AXIS FIFO depth. Timing may pass, but access to the registers will fail, returning 0x0000 and then ioctl error.
Status: Open
**Title:**iperf Test crashes the machine
**Type:**Open issue
Affected Projects/Modules: All projects
Description: For all projects, but mostly switch, when using iperf (2 or 3) and pushing enough traffic to trigger flow control, iperf may crash and crash the device with it (i.e. require reconfiguration). This happens only with iperf and not with other tools achieving similar bandwidth (e.g. mz, tcpreplay)
Status: Not intended to be further pursued
**Title:**Reduced Throughput
**Type:**Open Issue
**Affected Projects/Modules:**All
**Description:**Reference projects experience throughput that is less than optimal. For the reference_NIC this is largely caused by DMA. For the switch this is caused by 10G port flow control, and the basic pipeline design.
**Status:**Future enhancements
Title: Log file for acceptance test
Type: Information
**Affected Projects/Modules:**Acceptance test
Description: When you perform the acceptance test, if you close the testing GUI and reopen it, the file NfSumeTest.log is overwritten with the new tests.
Status: Future enhancement
Title: "Failed" acceptance tests
Type: Information
**Affected Projects/Modules:**Acceptance test
Description: Some of the tests (especially memory tests) may occasionally appear to fail. Usually this is due to the initialization of the memory calibration signals, not due to the malfunctioning of the components. Try repeating the tests and if tests repeatedly fail, then it might be a component failure. In this case, you should contact the supplier.
Status: Future enhancement
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