OSNT SUME Generator

IP Cores

• OSNT SUME IP cores
  • BRAM-Based PCAP Replay Engine
  • Inter Packet Delay
  • Rate Limiter
  • Extract Metadata
  • 10G TX Interfaces
• NetFPGA-SUME cores
  • RIFFA DMA
  • Input Arbiter
  • NIC Output Port Lookup
• Xilinx and Microblaze Subsystem
  • Xilinx AXI Peripheral
  • axi_interconnect
  • MicroBlaze
  • lmb_v10
  • lmb_bram_if_cntlr
  • bram_block
  • proc_sys_reset
  • clock_generator

Description

The OSNT SUME traffic generator generates packets according to pre-loaded PCAP traces. Currently, the system is designed based Xilinx embedded BRAM cores. The maximum trace dimension allowed strictly depends on the size of BRAM resources available on the FPGA. The system actually consists of four functional units: The Arbiter selects packets and forwards them at their departure time. The Delay Module (DM) and Rate Limiter (RL) control delay and rate for each flow. Finally, the packet is passed to the 10GbE Inteface which transmits it onto the wire.

The TX timestamp module (TS) is being used only in the [OSNT SUME](OSNT SUME) project (where also the RX Timestamp feature is enabled).

Future work

We are planning to integrate external memories (SRAM and DDR3 available on the SUME card) into the traffic generator that will allow users to load large number of PCAP traces.