OSNT Traffic Generator

Location

osnt/code/projects/osnt_generator

IP Cores

• OSNT Specific cores
  • PCAP Replay Engine
  • Inter Packet Delay
  • Rate Limiter
  • Extract Metadata
• NetFPGA-10G Specific cores
  • DMA
  • 10G MAC Interface
  • MDIO Engine
  • Input Arbiter
  • NIC Output Port Lookup
• Xilinx AXI Peripheral
  • axi_interconnect
• Microblaze Subsystem
  • MicroBlaze
  • lmb_v10
  • lmb_bram_if_cntlr
  • bram_block
  • proc_sys_reset
  • clock_generator

Description

The OSNT traffic generator generates packets according to pre-loaded PCAP traces. Currently, the system allows to select only one trace per port and where required reproduce it in a continuous loop. The maximum trace dimension allowed strictly depends on the SRAM resources available on board. The system actually consists of four functional units: The Arbiter selects packets and forwards them at their departure time. The Delay Module (DM) and Rate Limiter (RL) control delay and rate for each flow. Finally, the packet is passed to the (10GbE) MAC which transmits it onto the wire.

The TX timestamp module (TS) is being used only in the OSNT project (where also the RX Timestamp feature is enabled).

Future work

We are planning to implement several micro-engines, each of which generates traffic according to a given traffic model, list of flow values and data patterns from which we generate packet size, rate and inter-packet delays. In addition, we are planning to provide a Statistic Collector module for the received traffic.