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force bitfiles to be identical for same source code #2748

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6 changes: 5 additions & 1 deletion fpga/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,9 @@ XST_OPTS_AREA += -opt_level 2
XST_OPTS_AREA += -fsm_style bram
XST_OPTS_AREA += -fsm_encoding compact

# par specific option (set determistic seed)
PAR_OPTIONS = -t 1

# Types of selective module compilation:
# WITH_LF Enables selection of LF modules (and disables all HF)

Expand Down Expand Up @@ -179,12 +182,13 @@ work:
%.ncd: %_map.ncd
$(Q)$(RM) $@
$(info [-] PAR $@)
$(Q)$(XILINX_TOOLS_PREFIX)par $(VERBOSITY) -w $< $@
$(Q)$(XILINX_TOOLS_PREFIX)par $(PAR_OPTIONS) $(VERBOSITY) -w $< $@

%.bit: %.ncd
$(Q)$(RM) $@ $*.drc $*.rbt
$(info [=] BITGEN $@)
$(Q)$(XILINX_TOOLS_PREFIX)bitgen $(VERBOSITY) -w $* $@
echo "FFFFFFFFFFFFFFFFFFFFFF" | dd of=fpga_pm3_hf.bit bs=1 seek=48 conv=notrunc
$(Q)$(CP) $@ ..

# Build all targets
Expand Down
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