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Bluespec-2012.09.beta1B
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@ShepardSiegel
ShepardSiegel committed Sep 24, 2012
1 parent c865f5e commit 1622af6
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Showing 63 changed files with 24,708 additions and 8,415 deletions.
29 changes: 16 additions & 13 deletions libsrc/hdl/bsv/BRAM1.v
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Original file line number Diff line number Diff line change
@@ -1,5 +1,4 @@

// Copyright (c) 2000-2009 Bluespec, Inc.
// Copyright (c) 2000-2011 Bluespec, Inc.

// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
Expand All @@ -19,8 +18,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $
// $Revision: 28325 $
// $Date: 2012-04-25 18:22:57 +0000 (Wed, 25 Apr 2012) $

`ifdef BSV_ASSIGNMENT_DELAY
`else
Expand All @@ -41,7 +40,6 @@ module BRAM1(CLK,
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;


input CLK;
input EN;
input WE;
Expand All @@ -50,8 +48,8 @@ module BRAM1(CLK,
output [DATA_WIDTH-1:0] DO;

reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [ADDR_WIDTH-1:0] ADDR_R;
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DO_R2;

`ifdef BSV_NO_INITIAL_BLOCKS
`else
Expand All @@ -62,21 +60,26 @@ module BRAM1(CLK,
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
ADDR_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } };
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS

always @(posedge CLK) begin
if (EN) begin
if (WE)
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DI;
ADDR_R <= `BSV_ASSIGNMENT_DELAY ADDR;
if (WE) begin
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DI;
DO_R <= `BSV_ASSIGNMENT_DELAY DI;
end
else begin
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
end
end
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR_R];
DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;
end

assign DO = (PIPELINED) ? DO_R : RAM[ADDR_R];
// Output driver
assign DO = (PIPELINED) ? DO_R2 : DO_R;

endmodule // BRAM1
27 changes: 16 additions & 11 deletions libsrc/hdl/bsv/BRAM1BE.v
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
// Copyright (c) 2000-2009 Bluespec, Inc.
// Copyright (c) 2000-2011 Bluespec, Inc.

// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
Expand All @@ -18,8 +18,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $
// $Revision: 28325 $
// $Date: 2012-04-25 18:22:57 +0000 (Wed, 25 Apr 2012) $

`ifdef BSV_ASSIGNMENT_DELAY
`else
Expand Down Expand Up @@ -50,8 +50,8 @@ module BRAM1BE(CLK,
output [DATA_WIDTH-1:0] DO;

reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [ADDR_WIDTH-1:0] ADDR_R;
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DO_R2;

reg [DATA_WIDTH-1:0] DATA;
wire [DATA_WIDTH-1:0] DATAwr;
Expand All @@ -67,8 +67,8 @@ module BRAM1BE(CLK,
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
ADDR_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } };
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
Expand Down Expand Up @@ -104,13 +104,18 @@ module BRAM1BE(CLK,

always @(posedge CLK) begin
if (EN) begin
if (|WE)
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
ADDR_R <= `BSV_ASSIGNMENT_DELAY ADDR;
if (|WE) begin
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
DO_R <= `BSV_ASSIGNMENT_DELAY DATA;
end
else begin
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
end
end
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR_R];
DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;
end

assign DO = (PIPELINED) ? DO_R : RAM[ADDR_R];
// Output driver
assign DO = (PIPELINED) ? DO_R2 : DO_R;

endmodule // BRAM1BE
6 changes: 4 additions & 2 deletions libsrc/hdl/bsv/BRAM1Load.v
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Original file line number Diff line number Diff line change
Expand Up @@ -18,8 +18,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 25100 $
// $Date: 2011-09-01 18:44:19 +0000 (Thu, 01 Sep 2011) $
// $Revision: 28325 $
// $Date: 2012-04-25 18:22:57 +0000 (Wed, 25 Apr 2012) $

`ifdef BSV_ASSIGNMENT_DELAY
`else
Expand Down Expand Up @@ -53,6 +53,7 @@ module BRAM1Load(CLK,
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DO_R2;

// synopsys translate_off
initial
begin : init_block
`ifdef BSV_NO_INITIAL_BLOCKS
Expand All @@ -69,6 +70,7 @@ module BRAM1Load(CLK,
else
$readmemh(FILENAME, RAM, 0, MEMSIZE-1);
end
// synopsys translate_on

always @(posedge CLK) begin
if (EN) begin
Expand Down
48 changes: 24 additions & 24 deletions libsrc/hdl/bsv/BRAM2.v
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Original file line number Diff line number Diff line change
@@ -1,5 +1,4 @@

// Copyright (c) 2000-2009 Bluespec, Inc.
// Copyright (c) 2000-2011 Bluespec, Inc.

// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
Expand All @@ -19,15 +18,15 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $
// $Revision: 28325 $
// $Date: 2012-04-25 18:22:57 +0000 (Wed, 25 Apr 2012) $

`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif

// Dual-Ported BRAM (READ FIRST)
// Dual-Ported BRAM (WRITE FIRST)
module BRAM2(CLKA,
ENA,
WEA,
Expand Down Expand Up @@ -64,8 +63,8 @@ module BRAM2(CLKA,
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOB_R;
reg [DATA_WIDTH-1:0] DOA_D1_R;
reg [DATA_WIDTH-1:0] DOB_D1_R;
reg [DATA_WIDTH-1:0] DOA_R2;
reg [DATA_WIDTH-1:0] DOB_R2;

`ifdef BSV_NO_INITIAL_BLOCKS
`else
Expand All @@ -78,39 +77,40 @@ module BRAM2(CLKA,
end
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_D1_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_D1_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS

always @(posedge CLKA) begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
if (ENA) begin
if (WEA) begin
RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
end
RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
DOA_R <= `BSV_ASSIGNMENT_DELAY DIA;
end
else begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
end
end
DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
end

always @(posedge CLKB) begin
DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
if (ENB) begin
if (WEB) begin
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
end
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
DOB_R <= `BSV_ASSIGNMENT_DELAY DIB;
end
else begin
DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
end
end
DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
end

// Pipeline
always @(posedge CLKA)
DOA_D1_R <= DOA_R;

always @(posedge CLKB)
DOB_D1_R <= DOB_R;

// Output drivers
assign DOA = (PIPELINED) ? DOA_D1_R : DOA_R;
assign DOB = (PIPELINED) ? DOB_D1_R : DOB_R;
assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;

endmodule // BRAM2
51 changes: 30 additions & 21 deletions libsrc/hdl/bsv/ClockDiv.v
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@

// Copyright (c) 2000-2009 Bluespec, Inc.
// Copyright (c) 2000-2012 Bluespec, Inc.

// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
Expand All @@ -19,20 +19,29 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $

`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif


// A clock divider circuit.
// Division is based on the parameters, where
// Division is upper - lower + 1
// Duty cycle is :
// Duty cycle is :
// let half = 1 << (width-1)
// (upper - half) / upper - lower + 1
// (upper - half) / upper - lower + 1
// E.g., (2,1,3) is a divide by 3 duty cycle 2/3
// (2,0,3) is a divide by 4 duty cycle 2/4
// (1,0,1) is a divide by 2, duty cycle 1/2
Expand All @@ -41,17 +50,17 @@
// The offset allow edges for seperate modules to be determined
// relative to each other. a clock divider with offset 1 occurs one
// (fast) clock later than a clock with offset 0.
module ClockDiv(CLK_IN, RST_N, PREEDGE, CLK_OUT);
module ClockDiv(CLK_IN, RST, PREEDGE, CLK_OUT);

parameter width = 2 ; // must be sufficient to hold upper
parameter lower = 1 ; //
parameter lower = 1 ; //
parameter upper = 3 ;
parameter offset = 0; // offset for relative edges.
// (0 <= offset <= (upper - lower)

input CLK_IN; // input clock
input RST_N;
input RST;

output PREEDGE; // output signal announcing an upcoming edge
output CLK_OUT; // output clock

Expand All @@ -61,25 +70,25 @@ module ClockDiv(CLK_IN, RST_N, PREEDGE, CLK_OUT);
// Wire constants for the parameters
wire [width-1:0] upper_w ;
wire [width-1:0] lower_w ;

assign CLK_OUT = cntr[width-1] ;
assign upper_w = upper ;
assign lower_w = lower ;

// The clock is about to tick when counter is about to set its msb
// Note some simulators do not allow 0 width expressions
wire [width-1:0] nexttick = ~ ( 'b01 << (width-1) ) ;

// Combinational block to generate next edge signal
// Combinational block to generate next edge signal
always@( cntr or nexttick )
begin
#0
// The nonblocking assignment use to delay the update of the edge ready signal
// Since this read by other always blocks trigger by the output CLK of this module
PREEDGE <= `BSV_ASSIGNMENT_DELAY (cntr == nexttick) ;
end
always@( posedge CLK_IN or negedge RST_N )

always@( posedge CLK_IN or `BSV_RESET_EDGE RST )
begin
// The use of blocking assignment within this block insures
// that the clock generated from cntr[MSB] occurs before any
Expand All @@ -89,16 +98,16 @@ module ClockDiv(CLK_IN, RST_N, PREEDGE, CLK_OUT);
// updates occur. see
// http://www.sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf

if ( RST_N == 0 )
cntr = upper - offset ;
if ( RST == `BSV_RESET_VALUE )
cntr = upper - offset ;
else
begin
if ( cntr < upper_w )
cntr = cntr + 1 ;
else
cntr = lower_w ;
end // else: !if( RST_N == 0 )
end // always@ ( posedge CLK_IN or negedge RST_N )
end // else: !if( RST == `BSV_RESET_VALUE )
end // always@ ( posedge CLK_IN or `BSV_RESET_EDGE RST )

`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
Expand All @@ -107,8 +116,8 @@ module ClockDiv(CLK_IN, RST_N, PREEDGE, CLK_OUT);
begin
#0 ;
cntr = (upper - offset) ;
PREEDGE = 0 ;
end // initial begin
PREEDGE = 0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS

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