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Replace xme_ca_udm_dbg with xca_udm_dbg --aiearch aie-ml in the unit_tests/aievec_tests #546

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merged 4 commits into from
Jul 17, 2023

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Comment on lines 4 to 5
// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout
// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s
// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout
// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s
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Oh cool! I didn't know that worked. Is this the preferred way of running the aie2 simulator?

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@linay-xsj linay-xsj Jul 17, 2023

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xme_ca_udm_dbg is obsolete in the latest build. xca_udm_dbg --aiearch aie-ml is a preferred way of running the aie2 simulator now.

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With which version of Vitis does xca_udm_dbg --aiearch aie-ml start? I'm seeing errors related to this in my builds.

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daily_latest

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for 2022.2 use xme_ca_udm_dbg;
for 2023.1 and later use xca_udb_dbg --aiearch aie-ml

@linay-xsj linay-xsj merged commit 6723d6d into Xilinx:main Jul 17, 2023
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andrej pushed a commit to andrej/mlir-aie that referenced this pull request Jul 19, 2023
fifield added a commit to fifield/mlir-aie that referenced this pull request Nov 8, 2023
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4 participants