forked from verilator/verilator
-
Notifications
You must be signed in to change notification settings - Fork 3
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Merge pull request #28 from antmicro/randomize-constraints-crave-with
Support obj.randomize() with {...}- Loading branch information
Showing
11 changed files
with
201 additions
and
63 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Submodule crave
updated
6 files
| +21 −15 | CMakeLists.txt | |
| +12 −19 | examples/ALU/CMakeLists.txt | |
| +9 −2 | examples/CMakeLists.txt | |
| +1 −1 | metaSMT | |
| +2 −0 | src/lib/CMakeLists.txt | |
| +11 −4 | tests/CMakeLists.txt |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,21 @@ | ||
| #!/usr/bin/env perl | ||
| if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } | ||
| # DESCRIPTION: Verilator: Verilog Test driver/expect definition | ||
| # | ||
| # Copyright 2020 by Wilson Snyder. This program is free software; you | ||
| # can redistribute it and/or modify it under the terms of either the GNU | ||
| # Lesser General Public License Version 3 or the Perl Artistic License | ||
| # Version 2.0. | ||
| # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 | ||
|
|
||
| scenarios(simulator => 1); | ||
|
|
||
| compile( | ||
| ); | ||
|
|
||
| execute( | ||
| check_finished => 1, | ||
| ); | ||
|
|
||
| ok(1); | ||
| 1; |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,71 @@ | ||
| // DESCRIPTION: Verilator: Verilog Test module | ||
| // | ||
| // This file ONLY is placed under the Creative Commons Public Domain, for | ||
| // any use, without warranty, 2020 by Wilson Snyder. | ||
| // SPDX-License-Identifier: CC0-1.0 | ||
|
|
||
| typedef enum bit[15:0] { | ||
| ONE = 3, | ||
| TWO = 5, | ||
| THREE = 8, | ||
| FOUR = 13 | ||
| } Enum; | ||
|
|
||
| class Cls; | ||
| constraint A { v inside {ONE, THREE}; } | ||
| constraint B { w == 5; x inside {1,2} || x inside {4,5}; } | ||
| constraint C { z < 3 * 7; z > 5 + 8; } | ||
|
|
||
| rand Enum v; | ||
| rand logic[63:0] w; | ||
| rand logic[47:0] x; | ||
| rand logic[31:0] y; | ||
| rand logic[23:0] z; | ||
|
|
||
| function new; | ||
| v = ONE; | ||
| w = 0; | ||
| x = 0; | ||
| y = 0; | ||
| z = 0; | ||
| endfunction | ||
|
|
||
| endclass | ||
|
|
||
| module t (/*AUTOARG*/); | ||
| Cls obj; | ||
|
|
||
| initial begin | ||
| int rand_result; | ||
| int lb, ub; | ||
| longint prev_checksum; | ||
| $display("===================\nSatisfiable constraints:"); | ||
| for (int i = 0; i < 25; i++) begin | ||
| obj = new; | ||
| lb = 16; | ||
| ub = 32; | ||
| rand_result = obj.randomize() with { lb <= y && y <= ub; }; | ||
| $display("obj.v == %0d", obj.v); | ||
| $display("obj.w == %0d", obj.w); | ||
| $display("obj.x == %0d", obj.x); | ||
| $display("obj.y == %0d", obj.y); | ||
| $display("obj.z == %0d", obj.z); | ||
| $display("rand_result == %0d", rand_result); | ||
| $display("-------------------"); | ||
| if (!(obj.v inside {ONE, THREE})) $stop; | ||
| if (obj.w != 5) $stop; | ||
| if (!(obj.x inside {1,2,4,5})) $stop; | ||
| if (obj.y < 16 || obj.y > 32) $stop; | ||
| if (obj.z <= 13 || obj.z >= 21) $stop; | ||
| if (lb != 16 || ub != 32) $stop; | ||
| end | ||
| //$display("===================\nUnsatisfiable constraints for obj.y:"); | ||
| //rand_result = obj.randomize() with { 256 < y && y < 256; }; | ||
| //$display("obj.y == %0d", obj.y); | ||
| //$display("rand_result == %0d", rand_result); | ||
| //if (rand_result != 0) $stop; | ||
| //rand_result = obj.randomize() with { 16 <= z && z <= 32; }; | ||
| $write("*-* All Finished *-*\n"); | ||
| $finish; | ||
| end | ||
| endmodule |