dv test for mailbox accesses and wait testing #31
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Using elink0_mux_txwr_access to filter frames for elink0 and elink1_mux_rxwr_access for elink1 Tests can write to mailbox in elink0 or elink1 and read from mailbox in elink0 Adding WAIT parameter to elink1 the rx channel on elink1 backs up into the tx channel of elink0 MMU can also be used in both elink0 and elink1 if necessary Added simple memory testing with mailbox providing failure count feedback from core Signed-off-by: Peter Saunderson <[email protected]>
Signed-off-by: Peter Saunderson <[email protected]>
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Using elink0_mux_txwr_access to filter frames for elink0 and elink1_mux_rxwr_access for elink1
Tests can write to mailbox in elink0 or elink1 and read from mailbox in elink0
Adding WAIT parameter to elink1 the rx channel on elink1 backs up into the tx channel of elink0
MMU can also be used in both elink0 and elink1 if necessary
Added simple memory testing with mailbox providing failure count feedback from core
Signed-off-by: Peter Saunderson [email protected]