dv test for mailbox accesses and wait testing

elink/dv/test.memh

@@ -0,0 +1,71 @@
+00000000_00000003_810f0200_05_0040 //WRITE (E_RESET): assert reset (and wait!!!)
+00000000_00000000_810f0200_05_0100 //      (E_RESET): deassert reset (and wait more!!)
+00000000_00000810_810Ec880_05_0000 // E: EGROUP_MMU, 8 (c): RX, 4880: address 910, 0: mi_wr_vec = f lower four bytes - Writing to entry "910" lower
+00000000_00000000_810Ec884_05_0000 // E: EGROUP_MMU, 8 (c): RX, 4884: address 910, 4: mi_wr_vec = 30 upper two bytes - Writing to entry "910" upper ie 910 -> 810
+00000000_00000808_810Ec040_05_0000 // E: EGROUP_MMU, 8 (c): RX, 4040: 100 0 000 01address 808, 0: mi_wr_vec = f lower - Writing to entry "808"
+00000000_00000000_810Ec044_05_0000 // E: EGROUP_MMU, 8 (c): RX, 4044: address 808, 4: mi_wr_vec = 30 upper - ie 808 -> 808
+00000000_00000810_810Ec080_05_0000 // E: EGROUP_MMU, 8 (c): RX, 4080: address 810, 0: mi_wr_vec = f lower - Writing to entry "810"
+00000000_00000000_810Ec084_05_0000 // E: EGROUP_MMU, 8 (c): RX, 4084: address 810, 4: mi_wr_vec = 30 upper - ie 810 -> 808
+00000000_00000002_810f0300_05_0020 // Enable MMU
+00000000_00000820_820Ec900_05_0000 // E: EGROUP_MMU, 8 (c): RX, 4880: address 920, 0: mi_wr_vec = f lower four bytes - Writing to entry "920" lower
+00000000_00000000_820Ec904_05_0000 // E: EGROUP_MMU, 8 (c): RX, 4884: address 920, 4: mi_wr_vec = 30 upper two bytes - Writing to entry "920" upper ie 920 -> 820
+00000000_00000808_820Ec040_05_0000 // E: EGROUP_MMU, 8 (c): RX, 4040: 100 0 000 01address 808, 0: mi_wr_vec = f lower - Writing to entry "808"
+00000000_00000000_820Ec044_05_0000 // E: EGROUP_MMU, 8 (c): RX, 4044: address 808, 4: mi_wr_vec = 30 upper - ie 808 -> 808
+00000000_00000002_820f0300_05_0000 // Enable MMU 
+810D0204_00000001_810f0204_05_0000 //      (E_CLK): configure clock
+00000000_00000002_810f0208_05_0000 //      (E_CHIPID): write chipid
+00000000_0000AABB_810f020c_05_0000 //      (E_VERSION): write version
+00000000_00000000_810f0210_05_0000 //      (ETX_CFG): write TX config
+00000000_00000000_810f0214_05_0000 //      (ETX_STATUS): clear TX status
+00000000_810f1234_810f0218_05_0000 //      (ETX_GPIO): write tx gpio
+00000000_00000000_810F021c_05_0010 //zero out monitor
+00000000_00000000_810f0304_05_0000 //      (ERX_STATUS): clear RX status
+00000000_00000000_810f030C_05_0000 //      (ERX_OFFSET): offset register
+00000000_810f4321_810f0318_05_0000 //      (ERX_TESTDATA):test data
+00000000_808a5a51_80800000_05_0000 //32-bit write
+00000000_8085a5a2_80800004_05_0000 //32-bit write
+00000000_808a5a53_80800008_05_0000 //32-bit write
+00000000_80801014_8080000c_05_0000 //32-bit write
+00000000_80812125_80800010_05_0000 //32-bit write
+00000000_80823236_80800014_05_0000 //32-bit write
+00000000_80898397_80800018_05_0000 //32-bit write
+00000000_808ecec8_8080001c_05_0000 //32-bit write
+81000000_ff0a5a5a_910f0320_05_0000 // write mailbox 64bit: control mode 0; data mode 2'b10; write & ext_access
+810D0000_DEADBEEF_80800000_04_00f0 // dummy read?? - wait for all the Emem writes
+810D0000_DEADBEEF_80800000_04_0020 // cheat and allow multiple reads at once!
+810D0004_DEADBEEF_80800004_04_0020 //
+81000000_ff15a5a5_910f0320_05_0000 // write mailbox 64bit: control mode 0; data mode 2'b10; write & ext_access
+00000000_00000000_820f0304_05_0000 //      (elink1:ERX_STATUS): clear RX status
+82000000_EE145678_920f0320_05_0000 // elink1:write mailbox 64bit: control mode 0; data mode 2'b10; write & ext_access
+810D0008_DEADBEEF_80800008_04_0020 //
+00000000_FEDABEE1_810f0318_05_0000 //      (ERX_TESTDATA):test data
+810D000c_DEADBEEF_8080000c_04_0002 //
+82000000_EE287654_920f0320_05_0000 // elink1:write mailbox 64bit: control mode 0; data mode 2'b10; write & ext_access
+00000000_808cece9_80800020_05_0000 //32-bit write
+00000000_820f1111_820f0218_05_0000 //      (elink1:ETX_GPIO): write tx gpio
+810D0320_DEADBEEF_810f0320_04_0020 //      (E_MAILBOXLO): read from lo mailbox
+82000000_EE3a5a5a_920f0320_05_0000 // write mailbox 64bit: control mode 0; data mode 2'b10; write & ext_access
+00000000_808cecea_80800024_05_0000 //32-bit write
+810D0010_DEADBEEF_80800010_04_0020 //
+81000000_ff245678_910f0320_05_0000 // write mailbox 64bit: control mode 0; data mode 2'b10; write & ext_access
+82000000_EE145678_920f0320_05_0000 // elink1:write mailbox 64bit: control mode 0; data mode 2'b10; write & ext_access
+00000000_810f3292_810f0318_05_0000 //      (ERX_TESTDATA):test data
+810D0014_DEADBEEF_80800014_04_0020 //
+00000000_808abcdb_80800028_05_0000 //32-bit write
+810D0018_DEADBEEF_80800018_04_0020 //
+00000000_808dbcac_8080002c_05_0000 //32-bit write
+00000000_820f2222_820f0318_05_0000 //      (elink1:ERX_TESTDATA):test data
+810D001c_DEADBEEF_8080001c_04_0020 //
+810D0324_DEADFEEF_810f0324_04_0020 //      (E_MAILBOXHI): read from hi mailbox
+810D020C_DEADBEEF_810f020c_04_0020 //READ  (E_VERSION): read version
+810D0210_DEADBEEF_810f0210_04_0020 //      (ETX_CFG): read config
+810D0320_DEADBEEF_810f0320_04_0020 //      (E_MAILBOXLO): read from lo mailbox
+810D0324_DEADFEEF_810f0324_04_0020 //      (E_MAILBOXHI): read from hi mailbox
+810D0214_DEADBEEF_810f0214_04_0020 //      (ETX_STATUS): read status
+810D0218_DEADBEEF_810f0218_04_0020 //      (ETX_GPIO): read from tx gpio
+810D0300_DEADBEEF_810f0300_04_0020 //      (ERX_CFG): read from RX config
+810D0304_DEADBEEF_810f0304_04_0020 //      (ERX_STATUS): read from RX status
+810D0320_DEADBEEF_810f0320_04_0020 //      (E_MAILBOXLO): read from lo mailbox
+810D0324_DEADFEEF_810f0324_04_0020 //      (E_MAILBOXHI): read from hi mailbox
+810D0308_DEADFEEF_810f0308_04_0020 //      (ERX_GPIO): read from RX GPIO
+

elink/hdl/axi_elink.v

@@ -35,6 +35,9 @@ module axi_elink(/*AUTOARG*/
    parameter M_IDW       = 6;        //ID width for M_AXI
    parameter IOSTD_ELINK = "LVDS_25";
    parameter ETYPE       = 0;
+   parameter WAIT_RR     = 0;
+   parameter WAIT_WRRD   = 0;
+   parameter WAIT_CFG    = 0;
 
    /****************************/
    /*CLK AND RESET             */
@@ -217,6 +220,9 @@ module axi_elink(/*AUTOARG*/
    defparam elink.IOSTD_ELINK = IOSTD_ELINK;
    defparam elink.ETYPE       = ETYPE;
    defparam elink.ID          = ID;
+   defparam elink.WAIT_RR     = WAIT_RR;
+   defparam elink.WAIT_WRRD   = WAIT_WRRD;
+   defparam elink.WAIT_CFG    = WAIT_CFG;
 
    elink elink(
 	       /*AUTOINST*/

elink/hdl/elink.v

@@ -18,7 +18,10 @@ module elink (/*AUTOARG*/
    parameter ID          = 12'h810;  //epiphany ID for elink (ie addr[31:20])
    parameter IOSTD_ELINK = "LVDS_25";
    parameter ETYPE       = 1;
-
+   parameter WAIT_RR     = 0;
+   parameter WAIT_WRRD   = 0;
+   parameter WAIT_CFG    = 0;
+
    /****************************/
    /*MAIN CLOCK AND RESET      */
    /****************************/
@@ -149,7 +152,8 @@ module elink (/*AUTOARG*/
 
    defparam erx.ID          = ID;
    defparam erx.ETYPE       = ETYPE;
-
+   defparam erx.WAIT_RR     = WAIT_RR;
+   defparam erx.WAIT_WRRD   = WAIT_WRRD;
    erx erx(.rx_active			(elink_active),
 	   /*AUTOINST*/
 	   // Outputs
@@ -198,7 +202,8 @@ module elink (/*AUTOARG*/
 
    defparam etx.ID          = ID;
    defparam etx.ETYPE       = ETYPE;
-
+   defparam etx.WAIT_RR     = WAIT_RR;
+   defparam etx.WAIT_WRRD   = WAIT_WRRD;
    etx etx(
 	   /*AUTOINST*/
 	   // Outputs
@@ -240,6 +245,7 @@ module elink (/*AUTOARG*/
    /***********************************************************/
    defparam ecfg_cdc.DW=104;
    defparam ecfg_cdc.DEPTH=32;
+   defparam ecfg_cdc.WAIT = WAIT_CFG;
 
    oh_fifo_cdc ecfg_cdc (.nreset   	(erx_nreset),
 		      // Outputs

elink/hdl/erx.v

@@ -16,7 +16,9 @@ module erx (/*AUTOARG*/
    parameter RFAW        = 6;
    parameter ID          = 12'h800;
    parameter IOSTD_ELINK = "LVDS_25";
-   parameter ETYPE       = 1;   
+   parameter ETYPE       = 1;
+   parameter WAIT_RR     = 0;
+   parameter WAIT_WRRD   = 0;
 
    //Synched resets, clock
    input          soft_reset;                   // sw driven reset
@@ -176,7 +178,9 @@ module erx (/*AUTOARG*/
 
    /************************************************************/
    /*FIFOs                                                     */
-   /************************************************************/      
+   /************************************************************/
+   defparam erx_fifo.WAIT_RR = WAIT_RR;
+   defparam erx_fifo.WAIT_WRRD = WAIT_WRRD;
    erx_fifo erx_fifo   (
 		/*AUTOINST*/
 			// Outputs

elink/hdl/erx_fifo.v

@@ -12,6 +12,8 @@ module erx_fifo (/*AUTOARG*/
    parameter DW      = 32;
    parameter PW      = 104;
    parameter RFAW    = 6;
+   parameter WAIT_RR = 0;
+   parameter WAIT_WRRD = 0;
 
    //reset & clocks
    input 	   sys_clk;
@@ -76,8 +78,11 @@ module erx_fifo (/*AUTOARG*/
 
 
    //Read request fifo (from Epiphany)
-   oh_fifo_cdc #(.DW(104), .DEPTH(32)) 
-   rxrd_fifo   (
+   defparam rxrd_fifo.DW    = 104;
+   defparam rxrd_fifo.DEPTH = 32;
+   defparam rxrd_fifo.WAIT = WAIT_WRRD;
+
+   oh_fifo_cdc rxrd_fifo   (
 		/*AUTOINST*/
 		// Outputs
 		.wait_out		(rxrd_fifo_wait),	 // Templated
@@ -94,8 +99,11 @@ module erx_fifo (/*AUTOARG*/
 
 
    //Write fifo (from Epiphany)
-   oh_fifo_cdc #(.DW(104), .DEPTH(32)) 
-   rxwr_fifo(
+   defparam rxwr_fifo.DW    = 104;
+   defparam rxwr_fifo.DEPTH = 32;
+   defparam rxwr_fifo.WAIT  = WAIT_WRRD;
+
+   oh_fifo_cdc rxwr_fifo(
 	     /*AUTOINST*/
 	     // Outputs
 	     .wait_out			(rxwr_fifo_wait),	 // Templated
@@ -111,8 +119,11 @@ module erx_fifo (/*AUTOARG*/
 
 
    //Read response fifo (for host)
-   oh_fifo_cdc #(.DW(104), .DEPTH(32))  
-   rxrr_fifo(
+   defparam rxrr_fifo.DW    = 104;
+   defparam rxrr_fifo.DEPTH = 32;
+   defparam rxrr_fifo.WAIT  = WAIT_RR;
+
+   oh_fifo_cdc rxrr_fifo(
 	     /*AUTOINST*/
 	     // Outputs
 	     .wait_out			(rxrr_fifo_wait),	 // Templated

elink/hdl/etx.v

@@ -14,7 +14,9 @@ module etx(/*AUTOARG*/
    parameter PW          = 104;
    parameter RFAW        = 6;
    parameter ID          = 12'h000;
-   parameter ETYPE       = 0;   
+   parameter ETYPE       = 0;
+   parameter WAIT_RR     = 0;
+   parameter WAIT_WRRD   = 0;
 
    //Reset and clocks
    input 	  sys_clk;                      // clock for fifos      
@@ -106,6 +108,8 @@ module etx(/*AUTOARG*/
    /************************************************************/
    /*FIFOs                                                     */
    /************************************************************/
+   defparam etx_fifo.WAIT_RR = WAIT_RR;
+   defparam etx_fifo.WAIT_WRRD = WAIT_WRRD;
    etx_fifo etx_fifo (/*AUTOINST*/
 		      // Outputs
 		      .txrd_wait	(txrd_wait),

elink/hdl/etx_fifo.v

@@ -14,6 +14,8 @@ module etx_fifo(/*AUTOARG*/
    parameter PW      = 104;
    parameter RFAW    = 6;
    parameter ID      = 12'h000;
+   parameter WAIT_RR = 0;
+   parameter WAIT_WRRD = 0;
 
    //Clocks,reset,config
    input          sys_nreset;
@@ -77,7 +79,11 @@ module etx_fifo(/*AUTOARG*/
     */
 
    //Write fifo (from slave)
-   oh_fifo_cdc #(.DW(104), .DEPTH(32)) txwr_fifo(
+   defparam txwr_fifo.DW    = 104;
+   defparam txwr_fifo.DEPTH = 32;
+   //defparam txwr_fifo.WAIT = WAIT_WRRD;
+
+   oh_fifo_cdc txwr_fifo(
 			                  /*AUTOINST*/
 					      // Outputs
 					      .wait_out		(txwr_wait),	 // Templated
@@ -92,7 +98,11 @@ module etx_fifo(/*AUTOARG*/
 					      .wait_in		(txwr_fifo_wait)); // Templated
 
    //Read request fifo (from slave)
-   oh_fifo_cdc  #(.DW(104), .DEPTH(32)) txrd_fifo(
+   defparam txrd_fifo.DW    = 104;
+   defparam txrd_fifo.DEPTH = 32;
+   //defparam txrd_fifo.WAIT  = WAIT_WRRD;
+
+   oh_fifo_cdc txrd_fifo(
 				             /*AUTOINST*/
 					       // Outputs
 					       .wait_out	(txrd_wait),	 // Templated
@@ -109,7 +119,10 @@ module etx_fifo(/*AUTOARG*/
 
 
    //Read response fifo (from master)
-   oh_fifo_cdc  #(.DW(104), .DEPTH(32)) txrr_fifo(
+   defparam txrr_fifo.DW    = 104;
+   defparam txrr_fifo.DEPTH = 32;
+   //defparam txrr_fifo.WAIT  = WAIT_RR;
+   oh_fifo_cdc txrr_fifo(
 
 					     /*AUTOINST*/
 					       // Outputs

elink/sw/memory/build.sh

@@ -0,0 +1,26 @@
+#!/bin/bash
+
+set -e
+
+ESDK=${EPIPHANY_HOME}
+ELIBS="-L ${ESDK}/tools/host/lib"
+EINCS="-I ${ESDK}/tools/host/include"
+ELDF=${ESDK}/bsps/current/internal.ldf
+
+SCRIPT=$(readlink -f "$0")
+EXEPATH=$(dirname "$SCRIPT")
+cd $EXEPATH
+
+# Create the binaries directory
+mkdir -p bin/
+
+CROSS_PREFIX=
+
+# Build HOST side application
+${CROSS_PREFIX}gcc src/e-main.c -o bin/e-main.elf ${EINCS} ${ELIBS} -le-hal -le-loader -lpthread
+
+# Build DEVICE side program
+e-gcc -O0 -T ${ELDF} src/e-task.c -o bin/e-task.elf -le-lib -lm -ffast-math
+
+# Convert ebinary to SREC file
+e-objcopy --srec-forceS3 --output-target srec bin/e-task.elf bin/e-task.srec

elink/sw/memory/run.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+set -e
+
+SCRIPT=$(readlink -f "$0")
+EXEPATH=$(dirname "$SCRIPT")
+
+
+
+
+#dumping disassembly
+e-objdump -D bin/e-task.elf > DUMP
+
+#running program
+cd $EXEPATH/bin
+./e-main.elf e-task.elf
+

elink/sw/memory/src/common.h

@@ -0,0 +1,2 @@
+#define N    1024
+