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{bp-sim/arch} sim: fix sim smp boot regression #14066

Merged
merged 28 commits into from
Oct 10, 2024
Merged

{bp-sim/arch} sim: fix sim smp boot regression #14066

merged 28 commits into from
Oct 10, 2024

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jerpelea
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@jerpelea jerpelea commented Oct 10, 2024 •
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Summary

backported patches
#13609
#13695
#13810
#13768
#13808
#13737
#13766
#13811
#13749
#13863
#13933
#13735
#13739
#13908

Impact

RELEASE

Testing

CI

qinwei2004 and others added 23 commits October 10, 2024 16:04
@qinwei2004 @jerpelea
arm64: refine the fatal handler
91a3a07 
Summary
  The original implement for exception handler is very simple and
haven't framework for breakpoint/watchpoint routine or brk instruction.
  I refine the fatal handler and add framework for debug handler to
register or unregister. this is a prepare for watchpoint/breakpoint
implement

Signed-off-by: qinwei1 <[email protected]>
@qinwei2004 @jerpelea
arm64: add arm64_current_el to obtain current EL
cba9b89 
Summary
  Add a macro to obtain current execute level

Signed-off-by: qinwei1 <[email protected]>
@GUIDINGLI @jerpelea
arm64: save FPU regs every time
7935b82 
Signed-off-by: ligd <[email protected]>
@GUIDINGLI @jerpelea
arm64: simply the vectors
7216053 
Signed-off-by: ligd <[email protected]>
@lipengfei28 @jerpelea
Kernel build: enter exception save sp_sl0,exit exception restroe sp_el0
53bce2c 
Signed-off-by: lipengfei28 <[email protected]>
@pussuw @jerpelea
arm64_task/pthread_start: Set sp_el0 upon starting user process
b3083dd 
As the handling of sp_el0 was moved from the context switch routine
to exception entry/exit, we must set sp_el0 explicitly when the user
process is first started.
@szafonimateusz-mi @jerpelea
arch/x86_64/intel64/intel64_head.S: move initial RSP for AP cores bel…
9154299 
…ow regs area

move initial RSP for AP cores below regs area.
otherwise IDLE thread for AP cores can be corrupted

XCP region now match regs allocation in up_initial_state()

Signed-off-by: p-szafonimateusz <[email protected]>
@szafonimateusz-mi @jerpelea
arch/x86_64/intel64/intel64_cpuidlestack.c: stack_alloc should point …
0699813 
…to stack base not stack top

stack_alloc should point to stack base not stack top

Signed-off-by: p-szafonimateusz <[email protected]>
@szafonimateusz-mi @jerpelea
arch/x86_64/intel64/intel64_schedulesigaction.c: properly align signa…
f0bbd7f 
…l handler stack for vector operations

signal handler stack must be properly aligned, otherwise vector instructions doesn't work in signal handler

Signed-off-by: p-szafonimateusz <[email protected]>
@jasonbu @jerpelea
arch: cpu pause when sigaction only necessary if tcb running
b5467a1 
Signed-off-by: buxiasen <[email protected]>
@hujun260 @jerpelea
arch: move sigdeliver to common code
498be54 
Signed-off-by: hujun5 <[email protected]>
@hujun260 @jerpelea
signal: adjust the signal processing logic to remove the judgment
fc04650 
Signed-off-by: hujun5 <[email protected]>
@hujun260 @jerpelea
sched: replace sync pause with async pause for nxsig_process
c6e5dbb 
Signed-off-by: hujun5 <[email protected]>
@szafonimateusz-mi @jerpelea
arch/intel64: fix IRQ conflict with GOLDFISH
c6d7cad 
Also move MSI IRQ definition to place where other IRQ definitions are.

Signed-off-by: p-szafonimateusz <[email protected]>
@jerpelea
sched_smp:adjust the unlock order
b46cc4c 
1.nxsem_post wake up  nxsched_smp_call;
2.stack smp_call_data_s may return;
3.nxsched_smp_call_handler access call_data->lock is not safety;
so adjust the unlock order

Signed-off-by: dulibo1 <[email protected]>
@XuNeo @jerpelea
sched: handle sched lock in interrupt
ac2c32b 
Signed-off-by: xuxingliang <[email protected]>
@hujun260 @jerpelea
xtensa: add parameters to xtensa_pause_handler
020abf6 
reason:
nxsched_smp_call_handler need these parameters

Signed-off-by: hujun5 <[email protected]>
@szafonimateusz-mi @jerpelea
arch/intel64: colorize IDLE stack for AP cores
c2d078b 
colorize IDLE stack for AP cores in x86_64

Signed-off-by: p-szafonimateusz <[email protected]>
@hujun260 @jerpelea
x86_64: we should call x86_64_restorestate/x86_64_savestate
2f2b3f5 
reason:
In x86_64, g_current_regs is still used for context switching.

This commit fixes the regression from apache#13616

Signed-off-by: hujun5 <[email protected]>
@hujun260 @jerpelea
xtensa: Replace the implementation of up_cpu_pause
46dd8fa 
Signed-off-by: hujun5 <[email protected]>
@hujun260 @jerpelea
arch: remove up_cpu_pause up_cpu_resume up_cpu_paused up_cpu_pausereq
9a15a09 
reason:
  To remove the "sync pause" and decouple the critical section from the dependency on enabling interrupts,
  after that we need to further implement "schedlock + spinlock".
changelist
  1 Modify the implementation of critical sections to no longer involve enabling interrupts or handling synchronous pause events.
  2 GIC_SMP_CPUCALL attach to pause handler to remove arch interface up_cpu_paused_restore up_cpu_paused_save
  3 Completely remove up_cpu_pause, up_cpu_resume, up_cpu_paused, and up_cpu_pausereq
  4 change up_cpu_pause_async to up_send_cpu_sgi

Signed-off-by: hujun5 <[email protected]>
@hujun260 @jerpelea
arch: rename xxxx_pause.c to xxxx_smpcall.c
f71a065 
Signed-off-by: hujun5 <[email protected]>
@hujun260 @jerpelea
sim: fix sim smp boot regression
bb3d5e5 
This commit fixes the regression from apache#13716

Signed-off-by: hujun5 <[email protected]>
@github-actions github-actions bot added Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: avr Issues related to all AVR(8-bit or 32-bit) architectures Arch: ceva Issues related to CEVA architecture Arch: mips Issues related to the MIPS architecture Arch: openrisc Issues related to the OpenRISC architecture Arch: renesas Issues related to the Renesas chips labels Oct 10, 2024
@github-actions github-actions bot added Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: simulator Issues related to the SIMulator Arch: sparc Issues related to the SPARC architecture Arch: tricore Issues related to the TriCore architecture from Infineon Arch: x86 Issues related to the x86 architecture Arch: x86_64 Issues related to the x86_64 architecture Arch: xtensa Issues related to the Xtensa architecture Arch: z16 Issues related to the Z16 architecture Arch: z80 Issues related to the Z80 architecture Area: OS Components OS Components issues Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces. labels Oct 10, 2024
@github-actions GitHub Actions
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This PR exceeds the recommended size of 1000 lines. Please make sure you are NOT addressing multiple issues with one PR. Note this PR might be rejected due to its size.

@hujun260 @jerpelea
sched: replace sync pause with async pause for nxtask_restart
a0e0fe9 
reason:
In the kernel, we are planning to remove all occurrences of up_cpu_pause as one of the steps to
simplify the implementation of critical sections. The goal is to enable spin_lock_irqsave to encapsulate critical sections,
thereby facilitating the replacement of critical sections(big lock) with smaller spin_lock_irqsave(small lock)

Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic
-machine virt,virtualization=on,gic-version=3
-net none -chardev stdio,id=con,mux=on -serial chardev:con
-mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <[email protected]>
@github-actions GitHub Actions
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This PR exceeds the recommended size of 1000 lines. Please make sure you are NOT addressing multiple issues with one PR. Note this PR might be rejected due to its size.

XuNeo and others added 4 commits October 10, 2024 17:04
@XuNeo @jerpelea
assert: disable kasan in assert
8e43307 
Signed-off-by: Xu Xingliang <[email protected]>
@XuNeo @jerpelea
assert: cleanup assert handler
68bbff3 
1. extract dump from assert main flow
2. use OSINIT_PANIC for fatal error.
3. fix the method to judge kernel thread.

Signed-off-by: xuxingliang <[email protected]>
@XuNeo @jerpelea
assert: dump all CPU registers and stack
61ceadc 
Signed-off-by: xuxingliang <[email protected]>
@W-M-R @jerpelea
board_reset: flush cache before reset
ef1536b 
Signed-off-by: wangmingrong1 <[email protected]>
@github-actions GitHub Actions
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This PR exceeds the recommended size of 1000 lines. Please make sure you are NOT addressing multiple issues with one PR. Note this PR might be rejected due to its size.

@github-actions github-actions bot added the Area: Board support Board support issues label Oct 10, 2024
@github-actions GitHub Actions
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This PR exceeds the recommended size of 1000 lines. Please make sure you are NOT addressing multiple issues with one PR. Note this PR might be rejected due to its size.

@xiaoxiang781216 xiaoxiang781216 merged commit 0b98e9e into apache:releases/12.7 Oct 10, 2024
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Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: avr Issues related to all AVR(8-bit or 32-bit) architectures Arch: ceva Issues related to CEVA architecture Arch: mips Issues related to the MIPS architecture Arch: openrisc Issues related to the OpenRISC architecture Arch: renesas Issues related to the Renesas chips Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: simulator Issues related to the SIMulator Arch: sparc Issues related to the SPARC architecture Arch: tricore Issues related to the TriCore architecture from Infineon Arch: x86 Issues related to the x86 architecture Arch: x86_64 Issues related to the x86_64 architecture Arch: xtensa Issues related to the Xtensa architecture Arch: z16 Issues related to the Z16 architecture Arch: z80 Issues related to the Z80 architecture Area: Board support Board support issues Area: OS Components OS Components issues Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces.
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