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{bp-sim/arch} sim: fix sim smp boot regression #14066

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merged 28 commits into from
Oct 10, 2024
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91a3a07
arm64: refine the fatal handler
qinwei2004 Oct 30, 2023
cba9b89
arm64: add arm64_current_el to obtain current EL
qinwei2004 Oct 30, 2023
7935b82
arm64: save FPU regs every time
GUIDINGLI Sep 27, 2024
7216053
arm64: simply the vectors
GUIDINGLI Oct 1, 2024
53bce2c
Kernel build: enter exception save sp_sl0,exit exception restroe sp_el0
lipengfei28 Sep 12, 2024
b3083dd
arm64_task/pthread_start: Set sp_el0 upon starting user process
pussuw Oct 1, 2024
9154299
arch/x86_64/intel64/intel64_head.S: move initial RSP for AP cores bel…
szafonimateusz-mi Aug 30, 2024
0699813
arch/x86_64/intel64/intel64_cpuidlestack.c: stack_alloc should point …
szafonimateusz-mi Aug 30, 2024
f0bbd7f
arch/x86_64/intel64/intel64_schedulesigaction.c: properly align signa…
szafonimateusz-mi Aug 22, 2024
b5467a1
arch: cpu pause when sigaction only necessary if tcb running
jasonbu Aug 7, 2024
498be54
arch: move sigdeliver to common code
hujun260 Sep 11, 2024
fc04650
signal: adjust the signal processing logic to remove the judgment
hujun260 Sep 9, 2024
c6e5dbb
sched: replace sync pause with async pause for nxsig_process
hujun260 Sep 9, 2024
c6d7cad
arch/intel64: fix IRQ conflict with GOLDFISH
szafonimateusz-mi Sep 10, 2024
b46cc4c
sched_smp:adjust the unlock order
Apr 17, 2024
ac2c32b
sched: handle sched lock in interrupt
XuNeo Jul 16, 2024
020abf6
xtensa: add parameters to xtensa_pause_handler
hujun260 Sep 19, 2024
c2d078b
arch/intel64: colorize IDLE stack for AP cores
szafonimateusz-mi Sep 26, 2024
2f2b3f5
x86_64: we should call x86_64_restorestate/x86_64_savestate
hujun260 Sep 30, 2024
46dd8fa
xtensa: Replace the implementation of up_cpu_pause
hujun260 Oct 7, 2024
9a15a09
arch: remove up_cpu_pause up_cpu_resume up_cpu_paused up_cpu_pausereq
hujun260 Jul 29, 2024
f71a065
arch: rename xxxx_pause.c to xxxx_smpcall.c
hujun260 Sep 19, 2024
bb3d5e5
sim: fix sim smp boot regression
hujun260 Oct 8, 2024
a0e0fe9
sched: replace sync pause with async pause for nxtask_restart
hujun260 Sep 29, 2024
8e43307
assert: disable kasan in assert
XuNeo May 28, 2024
68bbff3
assert: cleanup assert handler
XuNeo Jul 17, 2024
61ceadc
assert: dump all CPU registers and stack
XuNeo Jul 16, 2024
ef1536b
board_reset: flush cache before reset
W-M-R Jul 30, 2024
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6 changes: 0 additions & 6 deletions arch/arm/include/arm/irq.h
Original file line number Diff line number Diff line change
Expand Up @@ -127,12 +127,6 @@
#ifndef __ASSEMBLY__
struct xcptcontext
{
/* The following function pointer is non-zero if there
* are pending signals to be processed.
*/

void *sigdeliver; /* Actual type is sig_deliver_t */

/* These are saved copies of the context used during
* signal processing.
*/
Expand Down
6 changes: 0 additions & 6 deletions arch/arm/include/armv6-m/irq.h
Original file line number Diff line number Diff line change
Expand Up @@ -152,12 +152,6 @@ struct xcpt_syscall_s

struct xcptcontext
{
/* The following function pointer is non-zero if there
* are pending signals to be processed.
*/

void *sigdeliver; /* Actual type is sig_deliver_t */

/* These are saved copies of the context used during
* signal processing.
*/
Expand Down
6 changes: 0 additions & 6 deletions arch/arm/include/armv7-a/irq.h
Original file line number Diff line number Diff line change
Expand Up @@ -253,12 +253,6 @@ struct xcpt_syscall_s

struct xcptcontext
{
/* The following function pointer is non-zero if there are pending signals
* to be processed.
*/

void *sigdeliver; /* Actual type is sig_deliver_t */

/* These are saved copies of the context used during
* signal processing.
*/
Expand Down
6 changes: 0 additions & 6 deletions arch/arm/include/armv7-m/irq.h
Original file line number Diff line number Diff line change
Expand Up @@ -212,12 +212,6 @@ struct xcpt_syscall_s

struct xcptcontext
{
/* The following function pointer is non-zero if there
* are pending signals to be processed.
*/

void *sigdeliver; /* Actual type is sig_deliver_t */

/* These are saved copies of the context used during
* signal processing.
*/
Expand Down
6 changes: 0 additions & 6 deletions arch/arm/include/armv7-r/irq.h
Original file line number Diff line number Diff line change
Expand Up @@ -253,12 +253,6 @@ struct xcpt_syscall_s

struct xcptcontext
{
/* The following function pointer is non-zero if there are pending signals
* to be processed.
*/

void *sigdeliver; /* Actual type is sig_deliver_t */

/* These are saved copies of the context used during
* signal processing.
*/
Expand Down
6 changes: 0 additions & 6 deletions arch/arm/include/armv8-m/irq.h
Original file line number Diff line number Diff line change
Expand Up @@ -223,12 +223,6 @@ struct xcpt_syscall_s

struct xcptcontext
{
/* The following function pointer is non-zero if there
* are pending signals to be processed.
*/

void *sigdeliver; /* Actual type is sig_deliver_t */

/* These are saved copies of the context used during
* signal processing.
*/
Expand Down
6 changes: 0 additions & 6 deletions arch/arm/include/armv8-r/irq.h
Original file line number Diff line number Diff line change
Expand Up @@ -253,12 +253,6 @@ struct xcpt_syscall_s

struct xcptcontext
{
/* The following function pointer is non-zero if there are pending signals
* to be processed.
*/

void *sigdeliver; /* Actual type is sig_deliver_t */

/* These are saved copies of the context used during
* signal processing.
*/
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/include/cxd56xx/irq.h
Original file line number Diff line number Diff line change
Expand Up @@ -158,7 +158,7 @@
#define CXD56_IRQ_SPH13 (CXD56_IRQ_EXTINT+93) /* SPH13 IRQ number */
#define CXD56_IRQ_SPH14 (CXD56_IRQ_EXTINT+94) /* SPH14 IRQ number */
#define CXD56_IRQ_SPH15 (CXD56_IRQ_EXTINT+95) /* SPH15 IRQ number */
#define CXD56_IRQ_SW_INT (CXD56_IRQ_EXTINT+96) /* SW_INT IRQ number */
#define CXD56_IRQ_SMP_CALL (CXD56_IRQ_EXTINT+96) /* SMP_CALL IRQ number */
#define CXD56_IRQ_TIMER0 (CXD56_IRQ_EXTINT+97) /* TIMER0 IRQ number */
#define CXD56_IRQ_TIMER1 (CXD56_IRQ_EXTINT+98) /* TIMER1 IRQ number */
#define CXD56_IRQ_TIMER2 (CXD56_IRQ_EXTINT+99) /* TIMER2 IRQ number */
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/include/lc823450/irq.h
Original file line number Diff line number Diff line change
Expand Up @@ -59,11 +59,11 @@
#define LC823450_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */

#define LC823450_IRQ_CTXM3_00 (LC823450_IRQ_INTERRUPTS+0) /* 16: CortexM3_00 interrupt */
#define LC823450_IRQ_CTXM3_01 (LC823450_IRQ_INTERRUPTS+1) /* 17: CortexM3_01 interrupt */
#define LC823450_IRQ_SMP_CALL_01 (LC823450_IRQ_INTERRUPTS+1) /* 17: CortexM3_01 interrupt */
#define LC823450_IRQ_CTXM3_02 (LC823450_IRQ_INTERRUPTS+2) /* 18: CortexM3_02 interrupt */
#define LC823450_IRQ_CTXM3_03 (LC823450_IRQ_INTERRUPTS+3) /* 19: CortexM3_03 interrupt */
#define LC823450_IRQ_CTXM3_10 (LC823450_IRQ_INTERRUPTS+4) /* 20: CortexM3_00 interrupt */
#define LC823450_IRQ_CTXM3_11 (LC823450_IRQ_INTERRUPTS+5) /* 21: CortexM3_01 interrupt */
#define LC823450_IRQ_SMP_CALL_11 (LC823450_IRQ_INTERRUPTS+5) /* 21: CortexM3_01 interrupt */
#define LC823450_IRQ_CTXM3_12 (LC823450_IRQ_INTERRUPTS+6) /* 22: CortexM3_02 interrupt */
#define LC823450_IRQ_CTXM3_13 (LC823450_IRQ_INTERRUPTS+7) /* 23: CortexM3_03 interrupt */
#define LC823450_IRQ_LPDSP0 (LC823450_IRQ_INTERRUPTS+8) /* 24: LPDSP0 interrupt */
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/include/rp2040/irq.h
Original file line number Diff line number Diff line change
Expand Up @@ -75,8 +75,8 @@
#define RP2040_DMA_IRQ_1 (RP2040_IRQ_EXTINT+12)
#define RP2040_IO_IRQ_BANK0 (RP2040_IRQ_EXTINT+13)
#define RP2040_IO_IRQ_QSPI (RP2040_IRQ_EXTINT+14)
#define RP2040_SIO_IRQ_PROC0 (RP2040_IRQ_EXTINT+15)
#define RP2040_SIO_IRQ_PROC1 (RP2040_IRQ_EXTINT+16)
#define RP2040_SMP_CALL_PROC0 (RP2040_IRQ_EXTINT+15)
#define RP2040_SMP_CALL_PROC1 (RP2040_IRQ_EXTINT+16)
#define RP2040_CLOCKS_IRQ (RP2040_IRQ_EXTINT+17)
#define RP2040_SPI0_IRQ (RP2040_IRQ_EXTINT+18)
#define RP2040_SPI1_IRQ (RP2040_IRQ_EXTINT+19)
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/include/sam34/sam4cm_irq.h
Original file line number Diff line number Diff line change
Expand Up @@ -114,15 +114,15 @@
#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+SAM_PID_TC5) /* PID 28: Timer Counter 5 */
#define SAM_IRQ_ADC (SAM_IRQ_EXTINT+SAM_PID_ADC) /* PID 29: Analog To Digital Converter */
#define SAM_IRQ_ARM (SAM_IRQ_EXTINT+SAM_PID_ARM) /* PID 30: FPU signals (only on CM4P1 core): FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */
#define SAM_IRQ_IPC0 (SAM_IRQ_EXTINT+SAM_PID_IPC0) /* PID 31: Interprocessor communication 0 */
#define SAM_IRQ_SMP_CALL0 (SAM_IRQ_EXTINT+SAM_PID_IPC0) /* PID 31: Interprocessor communication 0 */
#define SAM_IRQ_SLCDC (SAM_IRQ_EXTINT+SAM_PID_SLCDC) /* PID 32: Segment LCD Controller */
#define SAM_IRQ_TRNG (SAM_IRQ_EXTINT+SAM_PID_TRNG) /* PID 33: True Random Generator */
#define SAM_IRQ_ICM (SAM_IRQ_EXTINT+SAM_PID_ICM) /* PID 34: Integrity Check Module */
#define SAM_IRQ_CPKCC (SAM_IRQ_EXTINT+SAM_PID_CPKCC) /* PID 35: Classical Public Key Cryptography Controller */
#define SAM_IRQ_AES (SAM_IRQ_EXTINT+SAM_PID_AES) /* PID 36: Advanced Enhanced Standard */
#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* PID 37: Parallel I/O Controller C */
#define SAM_IRQ_UART1 (SAM_IRQ_EXTINT+SAM_PID_UART1) /* PID 38: Universal Asynchronous Receiver Transmitter 1 */
#define SAM_IRQ_IPC1 (SAM_IRQ_EXTINT+SAM_PID_IPC1) /* PID 39: Interprocessor communication 1 */
#define SAM_IRQ_SMP_CALL1 (SAM_IRQ_EXTINT+SAM_PID_IPC1) /* PID 39: Interprocessor communication 1 */
#define SAM_IRQ_RESERVED_40 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_40) /* PID 40: Reserved */
#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* PID 41: Pulse Width Modulation */
#define SAM_IRQ_SRAM (SAM_IRQ_EXTINT+SAM_PID_SRAM) /* PID 42: SRAM1 (I/D Code bus of CM4P1), SRAM2 (Systembus of CM4P1) */
Expand Down
6 changes: 0 additions & 6 deletions arch/arm/include/tlsr82/irq.h
Original file line number Diff line number Diff line change
Expand Up @@ -158,12 +158,6 @@
#ifndef __ASSEMBLY__
struct xcptcontext
{
/* The following function pointer is non-zero if there
* are pending signals to be processed.
*/

void *sigdeliver; /* Actual type is sig_deliver_t */

/* These are saved register array pointer used during
* signal processing.
*/
Expand Down
87 changes: 39 additions & 48 deletions arch/arm/src/arm/arm_schedulesigaction.c
Original file line number Diff line number Diff line change
Expand Up @@ -75,70 +75,61 @@
*
****************************************************************************/

void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
void up_schedule_sigaction(struct tcb_s *tcb)
{
sinfo("tcb=%p sigdeliver=%p\n", tcb, sigdeliver);
sinfo("tcb=%p, rtcb=%p current_regs=%p\n", tcb, this_task(),
this_task()->xcp.regs);

/* Refuse to handle nested signal actions */
/* First, handle some special cases when the signal is
* being delivered to the currently executing task.
*/

if (!tcb->xcp.sigdeliver)
if (tcb == this_task() && !up_interrupt_context())
{
tcb->xcp.sigdeliver = sigdeliver;
/* In this case just deliver the signal now. */

/* First, handle some special cases when the signal is
* being delivered to the currently executing task.
*/

sinfo("rtcb=%p current_regs=%p\n", this_task(),
this_task()->xcp.regs);

if (tcb == this_task() && !up_interrupt_context())
{
/* In this case just deliver the signal now. */
(tcb->sigdeliver)(tcb);
tcb->sigdeliver = NULL;
}

sigdeliver(tcb);
tcb->xcp.sigdeliver = NULL;
}
/* Otherwise, we are (1) signaling a task is not running
* from an interrupt handler or (2) we are not in an
* interrupt handler and the running task is signalling
* some non-running task.
*/

/* Otherwise, we are (1) signaling a task is not running
* from an interrupt handler or (2) we are not in an
* interrupt handler and the running task is signalling
* some non-running task.
else
{
/* Save the return lr and cpsr and one scratch register
* These will be restored by the signal trampoline after
* the signals have been delivered.
*/

else
{
/* Save the return lr and cpsr and one scratch register
* These will be restored by the signal trampoline after
* the signals have been delivered.
*/

/* Save the current register context location */
/* Save the current register context location */

tcb->xcp.saved_regs = tcb->xcp.regs;
tcb->xcp.saved_regs = tcb->xcp.regs;

/* Duplicate the register context. These will be
* restored by the signal trampoline after the signal has been
* delivered.
*/
/* Duplicate the register context. These will be
* restored by the signal trampoline after the signal has been
* delivered.
*/

tcb->xcp.regs = (void *)
((uint32_t)tcb->xcp.regs -
XCPTCONTEXT_SIZE);
memcpy(tcb->xcp.regs, tcb->xcp.saved_regs, XCPTCONTEXT_SIZE);
tcb->xcp.regs = (void *)
((uint32_t)tcb->xcp.regs -
XCPTCONTEXT_SIZE);
memcpy(tcb->xcp.regs, tcb->xcp.saved_regs, XCPTCONTEXT_SIZE);

tcb->xcp.regs[REG_SP] = (uint32_t)tcb->xcp.regs +
XCPTCONTEXT_SIZE;
tcb->xcp.regs[REG_SP] = (uint32_t)tcb->xcp.regs +
XCPTCONTEXT_SIZE;

/* Then set up to vector to the trampoline with interrupts
* disabled
*/
/* Then set up to vector to the trampoline with interrupts
* disabled
*/

tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
tcb->xcp.regs[REG_CPSR] = PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT;
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
tcb->xcp.regs[REG_CPSR] = PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT;
#ifdef CONFIG_ARM_THUMB
tcb->xcp.regs[REG_CPSR] |= PSR_T_BIT;
tcb->xcp.regs[REG_CPSR] |= PSR_T_BIT;
#endif
}
}
}
8 changes: 4 additions & 4 deletions arch/arm/src/arm/arm_sigdeliver.c
Original file line number Diff line number Diff line change
Expand Up @@ -59,8 +59,8 @@ void arm_sigdeliver(void)
board_autoled_on(LED_SIGNAL);

sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
DEBUGASSERT(rtcb->xcp.sigdeliver != NULL);
rtcb, rtcb->sigdeliver, rtcb->sigpendactionq.head);
DEBUGASSERT(rtcb->sigdeliver != NULL);

#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* Then make sure that interrupts are enabled. Signal handlers must always
Expand All @@ -72,7 +72,7 @@ void arm_sigdeliver(void)

/* Deliver the signal */

((sig_deliver_t)rtcb->xcp.sigdeliver)(rtcb);
(rtcb->sigdeliver)(rtcb);

/* Output any debug messages BEFORE restoring errno (because they may
* alter errno), then disable interrupts again and restore the original
Expand All @@ -92,7 +92,7 @@ void arm_sigdeliver(void)
* could be modified by a hostile program.
*/

rtcb->xcp.sigdeliver = NULL; /* Allows next handler to be scheduled */
rtcb->sigdeliver = NULL; /* Allows next handler to be scheduled */

/* Then restore the correct state for this thread of execution. */

Expand Down
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