Add Rev3 EMP Configs

.ipbb_setup.yml

@@ -1,11 +1,18 @@
 init:
   - make init
-  - make list 
-  - make prebuild_EMP_Cornell_rev2_p1_VU13p-1-SM_USP
-  - make address_table_EMP_Cornell_rev2_p1_VU13p-1-SM_USP
-  - make prebuild_EMP_Cornell_rev2_p2_VU13p-1-SM_USP
-  - make address_table_EMP_Cornell_rev2_p2_VU13p-1-SM_USP
-
+  - make list
+  # - make prebuild_EMP_Cornell_rev2_p1_VU13p-1-SM_USP
+  # - make address_table_EMP_Cornell_rev2_p1_VU13p-1-SM_USP
+  # - make prebuild_EMP_Cornell_rev2_p2_VU13p-1-SM_USP
+  # - make address_table_EMP_Cornell_rev2_p2_VU13p-1-SM_USP
+  # - make prebuild_EMP_Cornell_rev3_p1_VU13p-1-SM_USP
+  # - make address_table_EMP_Cornell_rev3_p1_VU13p-1-SM_USP
+  # - make prebuild_EMP_Cornell_rev3_p2_VU13p-1-SM_USP
+  # - make address_table_EMP_Cornell_rev3_p2_VU13p-1-SM_USP
+# JRF to speed things up, these targets should be generated dymanically by ipbb
+# and then the build would take 1/4 of the time to build.
+# For now I have moved these to the CI script so that it can build the precise
+# Targets
 
 reset:
   - git submodule deinit -f .

configs/EMP_Cornell_rev3_p1_VU13p-1-SM_USP/config.yaml

@@ -0,0 +1,57 @@
+AXI_CONTROL_SETS:
+  INCLUDE_FILE:  ${::apollo_root_path}/src/CM_yaml/CM1_base.yaml
+  # override default axilite endpoint
+  AXILITE_ENDPOINT_CTRL:
+    axi_interconnect: "${::CM_INTERCONNECT}"
+    axi_clk: "${::AXI_MASTER_CLK}"
+    axi_rstn: "/SYS_RESET/peripheral_aresetn"
+    axi_freq: "${::AXI_MASTER_CLK_FREQ}"
+    allocator:
+      starting_address: 0xB1000000
+      size: 0x00800000
+      block_size: 4K
+
+AXI_SLAVES:
+  BASE:
+    INCLUDE_FILE: ${::apollo_root_path}/src/CM_yaml/EMP_base.yaml
+    SUB_SLAVES:
+      C2C:
+        INCLUDE_FILE: ${::apollo_root_path}/src/CM_yaml/CM_C2C/Cornell_rev2_p1_C2C.yaml
+      F1_IPBUS:
+        TCL_CALL:
+          command: AXI_PL_DEV_CONNECT 
+          axi_control: "${::AXI_ENDPOINT_CTRL}"
+          type: "AXI4"
+          addr:
+            offset: "-1"
+            range:  "16M"
+          data_width: "64"
+          remote_slave: "1"
+        XML: "address_table/modules/IPBUS.xml"
+        UHAL_BASE: "auto"
+      F1_IO:
+        TCL_CALL: 
+          command: AXI_PL_DEV_CONNECT
+          axi_control: "${::AXILITE_ENDPOINT_CTRL}"
+          addr:
+            offset: "-1"
+            range: "4K"
+          remote_slave: "1"
+        XML: "address_table/modules/CM_IO_EMP.xml"
+        UHAL_BASE: "auto"
+        HDL: 
+          out_name: "IO"
+          map_template: "axi_generic/template_map_withbram.vhd"
+      F1_CM_FW_INFO:
+        TCL_CALL:
+          command: AXI_PL_DEV_CONNECT 
+          axi_control: "${::AXILITE_ENDPOINT_CTRL}"
+          addr:
+            offset: "-1"
+            range: "4K"
+          remote_slave: "1"
+        XML: "address_table/modules/FW_INFO.xml"
+        UHAL_BASE: "auto"
+        HDL: 
+          out_name: "CM_FW_INFO"
+          map_template: "axi_generic/template_map.vhd"

configs/EMP_Cornell_rev3_p1_VU13p-1-SM_USP/files_emp.dep

@@ -0,0 +1,46 @@
+setup ../../../../src/CM_yaml/CM_C2C/createC2CSlaveInterconnect.tcl
+setup -c emp-fwk:boards/apollo/common ../cfg/apollo_set_paths.tcl
+
+
+
+src ../../src/sub_module.vhd 
+
+
+src ../../../../src/misc/pacd.vhd 
+src ../../../../src/misc/types.vhd 
+src ../../../../src/misc/capture_CDC.vhd 
+src ../../../../src/misc/rate_counter.vhd 
+src ../../../../src/misc/counter.vhd 
+src ../../../../src/misc/capture_CDC.vhd 
+src ../../../../src/misc/uart.vhd 
+
+src ../../../../src/RGB_PWM.vhd 
+src ../../../../src/LED_PWM.vhd   
+
+src ../../../../regmap_helper/axiReg/axiRegWidthPkg_32.vhd
+src ../../../../regmap_helper/axiReg/axiRegPkg_d64.vhd 
+src ../../../../regmap_helper/axiReg/axiRegPkg.vhd 
+src ../../../../regmap_helper/axiReg/axiReg.vhd 
+src ../../../../regmap_helper/axiReg/axiRegBlocking.vhd
+src ../../../../regmap_helper/axiReg/bramPortPkg.vhd
+
+src ../../../../src/C2C_INTF/CM_phy_lane_control.vhd
+src ../../../../src/C2C_INTF/picoblaze/uC.vhd
+src ../../../../src/C2C_INTF/picoblaze/kcpsm6.vhd
+src ../../../../src/C2C_INTF/picoblaze/uart_tx6.vhd
+src ../../../../src/C2C_INTF/picoblaze/uart_rx6.vhd
+src ../../../../src/C2C_INTF/picoblaze/picoblaze/cli.vhd
+src ../../../../src/C2C_INTF/C2C_Intf.vhd
+
+src ../../../../src/CM_FW_info/CM_FW_info.vhd
+
+src ../../autogen/CM_FW_INFO/CM_FW_INFO_PKG.vhd
+src ../../autogen/CM_FW_INFO/CM_FW_INFO_map.vhd
+src ../../autogen/C2C_INTF/C2C_INTF_map.vhd
+src ../../autogen/C2C_INTF/C2C_INTF_PKG.vhd
+src ../../autogen/IO/IO_map.vhd
+src ../../autogen/IO/IO_PKG.vhd
+#src ../../autogen/Global_PKG.vhd
+
+
+

configs/EMP_Cornell_rev3_p1_VU13p-1-SM_USP/settings.tcl

@@ -0,0 +1,19 @@
+
+#set the FPGA part number
+set FPGA_part xcvu13p-flga2577-1-e
+
+##for c2c
+set C2C F1_C2C
+set C2C_PHY ${C2C}_PHY
+set C2CB F1_C2CB
+set C2CB_PHY ${C2CB}_PHY
+
+#create remote device tree entries, 64 bit
+global REMOTE_C2C_64
+set REMOTE_C2C_64 1
+
+
+set top top
+
+set outputDir ./
+