build(deps): bump third_party/cores/opentitan from eec48c4 to 913c56f
#6247
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Bumps [third_party/cores/opentitan](https://github.com/lowRISC/opentitan) from `eec48c4` to `913c56f`. - [Release notes](https://github.com/lowRISC/opentitan/releases) - [Commits](lowRISC/opentitan@eec48c4...913c56f) --- updated-dependencies: - dependency-name: third_party/cores/opentitan dependency-type: direct:production ... Signed-off-by: dependabot[bot] <[email protected]>
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Superseded by #6260. |
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Bumps third_party/cores/opentitan from
eec48c4to913c56f.Commits
913c56f[sival, keymgr] State-agnostic chip_sw_key_derivation_testa1f03a7[keymgr] Remove unused includes in keymgr_key_derivation_test.c9a5edd3[repo] Adjust BLOCKFILE to apply only to specific blocks42fdcae[rv_dm,dv] Slightly broaden dependency in rv_dm_env.cored4b4799[hw,mbx,rtl] Gate TLUL error with valid signalcbf2b24[dv, dvsim] stability fixes for the nc job scheduler5018ada[prim,fpga] Add FPGA-specific primitive implementations for prim_xnor2264c73b[pre_syn] Fix Yosys synthesis flows for AES, KMAC, OTBN7e76fe2[topgen] Make toplevel SV and chiplevel templates top-sepcificd0f3500[spi_host, dv] : Add missing argument for format specificationDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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