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refactor ipemu probes #703

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Aug 9, 2024
Merged

refactor ipemu probes #703

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7b59526
[ipemu] refactor probe signatures to improve readability
Clo91eaf Aug 6, 2024
3be38a1
[ipemu] refactor to an single Probe to avoid using Record
Clo91eaf Aug 6, 2024
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24 changes: 8 additions & 16 deletions ipemu/src/TestBench.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -190,32 +190,24 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])

// Events for difftest and performance modeling

val laneProbes = dut.io.laneProbes.zipWithIndex.map {
case (p, idx) =>
val wire = Wire(p.cloneType).suggestName(s"lane${idx}Probe")
wire := probe.read(p)
wire
// Probes
val laneProbes = t1Probe.laneProbes.zipWithIndex.map {
case (lane, i) => lane.suggestName(s"lane${i}Probe")
}

val lsuProbe = probe.read(dut.io.lsuProbe).suggestName("lsuProbe")
val lsuProbe = t1Probe.lsuProbe.suggestName("lsuProbe")

val storeUnitProbe = lsuProbe.storeUnitProbe.suggestName("storeUnitProbe")

val otherUnitProbe = lsuProbe.otherUnitProbe.suggestName("otherUnitProbe")

val laneVrfProbes = dut.io.laneVrfProbes.zipWithIndex.map {
case (p, idx) =>
val wire = Wire(p.cloneType).suggestName(s"lane${idx}VrfProbe")
wire := probe.read(p)
wire
}

// vrf write
laneVrfProbes.zipWithIndex.foreach {
laneProbes.zipWithIndex.foreach {
case (lane, i) =>
when(lane.valid)(
val vrf = lane.vrfProbe.suggestName(s"lane${i}VrfProbe")
when(vrf.valid)(
printf(
cf"""{"event":"VrfWrite","issue_idx":${lane.requestInstruction},"vd":${lane.requestVd},"offset":${lane.requestOffset},"mask":"${lane.requestMask}%x","data":"${lane.requestData}%x","lane":$i,"cycle":${simulationTime}}\n"""
cf"""{"event":"VrfWrite","issue_idx":${vrf.requestInstruction},"vd":${vrf.requestVd},"offset":${vrf.requestOffset},"mask":"${vrf.requestMask}%x","data":"${vrf.requestData}%x","lane":$i,"cycle":${simulationTime}}\n"""
)
)
}
Expand Down
46 changes: 17 additions & 29 deletions t1/src/Lane.scala
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Expand Up @@ -27,7 +27,7 @@ class LaneOM extends Class {
vfus := vfusIn
}

class LaneSlotProbe(instructionIndexBit: Int) extends Bundle {
class LaneSlotProbe(instructionIndexBits: Int) extends Bundle {
val stage0EnqueueReady: Bool = Bool()
val stage0EnqueueValid: Bool = Bool()
val changingMaskSet: Bool = Bool()
Expand All @@ -44,29 +44,26 @@ class LaneSlotProbe(instructionIndexBit: Int) extends Bundle {

// write queue enq for lane
val writeQueueEnq: Bool = Bool()
val writeTag: UInt = UInt(instructionIndexBit.W)
val writeTag: UInt = UInt(instructionIndexBits.W)
val writeMask: UInt = UInt(4.W)
}

class LaneWriteProbe(instructionIndexBit: Int) extends Bundle {
val writeTag: UInt = UInt(instructionIndexBit.W)
class LaneWriteProbe(instructionIndexBits: Int) extends Bundle {
val writeTag: UInt = UInt(instructionIndexBits.W)
val writeMask: UInt = UInt(4.W)
}

class LaneProbe(slotsSize: Int, instructionIndexBit: Int) extends Bundle {
val slots = Vec(slotsSize, new LaneSlotProbe(instructionIndexBit))
// @todo @Clo91eaf remove valid here, add stall := valid & !ready
val laneRequestValid: Bool = Bool()
// @todo remove it.
val laneRequestReady: Bool = Bool()
class LaneProbe(parameter: LaneParameter) extends Bundle {
val slots = Vec(parameter.chainingSize, new LaneSlotProbe(parameter.instructionIndexBits))
val laneRequestStall: Bool = Bool()
// @todo @Clo91eaf change to occupied for each slot.
val lastSlotOccupied: Bool = Bool()
// @todo replace it with VRFProbe
val vrfInstructionWriteReportReady: Bool = Bool()
val instructionFinished: UInt = UInt(slotsSize.W)
val instructionValid: UInt = UInt(slotsSize.W)
val instructionFinished: UInt = UInt(parameter.chainingSize.W)
val instructionValid: UInt = UInt(parameter.chainingSize.W)

val crossWriteProbe: Vec[ValidIO[LaneWriteProbe]] = Vec(2, Valid(new LaneWriteProbe(parameter.instructionIndexBits)))

val crossWriteProbe: Vec[ValidIO[LaneWriteProbe]] = Vec(2, Valid(new LaneWriteProbe(instructionIndexBit)))
val vrfProbe: VRFProbe = new VRFProbe(parameter.vrfParam)
}

object LaneParameter {
Expand Down Expand Up @@ -314,16 +311,9 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
val vrfReadyToStore: Bool = IO(Output(Bool()))

@public
val probe: LaneProbe = IO(Output(Probe(new LaneProbe(parameter.chainingSize, parameter.instructionIndexBits))))
val probeWire: LaneProbe = Wire(new LaneProbe(parameter.chainingSize, parameter.instructionIndexBits))
define(probe, ProbeValue(probeWire))
@public
val vrfProbe = IO(Output(Probe(new VRFProbe(
parameter.vrfParam.regNumBits,
parameter.vrfOffsetBits,
parameter.instructionIndexBits,
parameter.datapathWidth
))))
val laneProbe = IO(Output(Probe(new LaneProbe(parameter))))
val probeWire = Wire(new LaneProbe(parameter))
define(laneProbe, ProbeValue(probeWire))

@public
val vrfAllocateIssue: Bool = IO(Output(Bool()))
Expand All @@ -333,7 +323,6 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[

/** VRF instantces. */
val vrf: Instance[VRF] = Instantiate(new VRF(parameter.vrfParam))
define(vrfProbe, vrf.probe)

/** TODO: review later
*/
Expand Down Expand Up @@ -1222,15 +1211,14 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
tokenManager.topWriteDeq.bits := allVrfWriteAfterCheck(parameter.chainingSize).instructionIndex

// probe wire
probeWire.laneRequestValid := laneRequest.valid
probeWire.laneRequestReady := laneRequest.ready
probeWire.laneRequestStall := laneRequest.valid && !laneRequest.ready
probeWire.lastSlotOccupied := slotOccupied.last
probeWire.vrfInstructionWriteReportReady := vrf.instructionWriteReport.ready
probeWire.instructionFinished := instructionFinished
probeWire.instructionValid := instructionValid
probeWire.crossWriteProbe.zip(writeBusPort).foreach {case (pb, port) =>
pb.valid := port.deq.valid
pb.bits.writeTag := port.deq.bits.instructionIndex
pb.bits.writeMask := port.deq.bits.mask
}
probeWire.vrfProbe := probe.read(vrf.vrfProbe)
}
40 changes: 13 additions & 27 deletions t1/src/T1.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -292,18 +292,21 @@ case class T1Parameter(
def adderParam: LaneAdderParam = LaneAdderParam(datapathWidth, 0)
}

class T1Probe(param: T1Parameter) extends Bundle {
val instructionCounter: UInt = UInt(param.instructionIndexBits.W)
class T1Probe(parameter: T1Parameter) extends Bundle {
val instructionCounter: UInt = UInt(parameter.instructionIndexBits.W)
val instructionIssue: Bool = Bool()
val issueTag: UInt = UInt(param.instructionIndexBits.W)
val issueTag: UInt = UInt(parameter.instructionIndexBits.W)
val retireValid: Bool = Bool()
// write queue enq for mask unit
val writeQueueEnq: ValidIO[UInt] = Valid(UInt(param.instructionIndexBits.W))
val writeQueueEnqMask: UInt = UInt((param.datapathWidth / 8).W)
val writeQueueEnq: ValidIO[UInt] = Valid(UInt(parameter.instructionIndexBits.W))
val writeQueueEnqMask: UInt = UInt((parameter.datapathWidth / 8).W)
// mask unit instruction valid
val instructionValid: UInt = UInt((param.chainingSize * 2).W)
val instructionValid: UInt = UInt((parameter.chainingSize * 2).W)
// instruction index for check rd
val responseCounter: UInt = UInt(param.instructionIndexBits.W)
val responseCounter: UInt = UInt(parameter.instructionIndexBits.W)
// probes
val lsuProbe: LSUProbe = new LSUProbe(parameter.lsuParameters)
val laneProbes: Vec[LaneProbe] = Vec(parameter.laneNumber, new LaneProbe(parameter.laneParam))
}

class T1Interface(parameter: T1Parameter) extends Record {
Expand All @@ -314,11 +317,7 @@ class T1Interface(parameter: T1Parameter) extends Record {
def highBandwidthLoadStorePort: AXI4RWIrrevocable = elements("highBandwidthLoadStorePort").asInstanceOf[AXI4RWIrrevocable]
def indexedLoadStorePort: AXI4RWIrrevocable = elements("indexedLoadStorePort").asInstanceOf[AXI4RWIrrevocable]
def om: Property[ClassType] = elements("om").asInstanceOf[Property[ClassType]]
// TODO: refactor to an single Probe to avoid using Record on the [[T1Interface]].
def lsuProbe: LSUProbe = elements("lsuProbe").asInstanceOf[LSUProbe]
def t1Probe: T1Probe = elements("t1Probe").asInstanceOf[T1Probe]
def laneProbes: Seq[LaneProbe] = Seq.tabulate(parameter.laneNumber)(i => elements(s"lane${i}Probe").asInstanceOf[LaneProbe])
def laneVrfProbes: Seq[VRFProbe] = Seq.tabulate(parameter.laneNumber)(i => elements(s"lane${i}VrfProbe").asInstanceOf[VRFProbe])
val elements: SeqMap[String, Data] = SeqMap.from(
Seq(
"clock" -> Input(Clock()),
Expand All @@ -328,15 +327,8 @@ class T1Interface(parameter: T1Parameter) extends Record {
"highBandwidthLoadStorePort" -> new AXI4RWIrrevocable(parameter.axi4BundleParameter),
"indexedLoadStorePort" -> new AXI4RWIrrevocable(parameter.axi4BundleParameter.copy(dataWidth=32)),
"om" -> Output(Property[AnyClassType]()),
"lsuProbe" -> Output(Probe(new LSUProbe(parameter.lsuParameters))),
"t1Probe" -> Output(Probe(new T1Probe(parameter))),
) ++
Seq.tabulate(parameter.laneNumber)(
i => s"lane${i}Probe" -> Output(Probe(new LaneProbe(parameter.chainingSize, parameter.instructionIndexBits)))
) ++
Seq.tabulate(parameter.laneNumber)(
i => s"lane${i}VrfProbe" -> Output(Probe(new VRFProbe(parameter.laneParam.vrfParam.regNumBits, parameter.laneParam.vrfOffsetBits, parameter.laneParam.instructionIndexBits, parameter.laneParam.datapathWidth)))
)
)
)
}

Expand Down Expand Up @@ -1583,15 +1575,7 @@ class T1(val parameter: T1Parameter)
lane
}

laneVec.zipWithIndex.foreach { case (lane, index) =>
define(io.laneProbes(index), lane.probe)
define(io.laneVrfProbes(index), lane.vrfProbe)
}

omInstance.lanesIn := Property(laneVec.map(_.om.asAnyClassType))

define(io.lsuProbe, lsu._probe)

dataInWritePipeVec := VecInit(laneVec.map(_.writeQueueValid))

// 连lsu
Expand Down Expand Up @@ -1745,6 +1729,8 @@ class T1(val parameter: T1Parameter)
!slots.last.state.sMaskUnitExecution && !slots.last.state.idle,
indexToOH(slots.last.record.instructionIndex, parameter.chainingSize * 2)).asUInt
probeWire.responseCounter := responseCounter
probeWire.laneProbes.zip(laneVec).foreach { case (p, l) => p := probe.read(l.laneProbe) }
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probeWire.lsuProbe := probe.read(lsu.lsuProbe)


// new V Request from core
Expand Down
4 changes: 2 additions & 2 deletions t1/src/lsu/LSU.scala
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Expand Up @@ -246,9 +246,9 @@ class LSU(param: LSUParameter) extends Module {
)

@public
val _probe = IO(Output(Probe(new LSUProbe(param))))
val lsuProbe = IO(Output(Probe(new LSUProbe(param))))
val probeWire = Wire(new LSUProbe(param))
define(_probe, ProbeValue(probeWire))
define(lsuProbe, ProbeValue(probeWire))

// read vrf
val otherTryReadVrf: UInt = Mux(otherUnit.vrfReadDataPorts.valid, otherUnit.status.targetLane, 0.U)
Expand Down
18 changes: 9 additions & 9 deletions t1/src/vrf/VRF.scala
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Expand Up @@ -106,13 +106,13 @@ case class VRFParam(
val vrfReadLatency = 2
}

class VRFProbe(regNumBits: Int, offsetBits: Int, instructionIndexSize: Int, dataPathWidth: Int) extends Bundle {
class VRFProbe(parameter: VRFParam) extends Bundle {
val valid: Bool = Bool()
val requestVd: UInt = UInt(regNumBits.W)
val requestOffset: UInt = UInt(offsetBits.W)
val requestMask: UInt = UInt((dataPathWidth / 8).W)
val requestData: UInt = UInt(dataPathWidth.W)
val requestInstruction: UInt = UInt(instructionIndexSize.W)
val requestVd: UInt = UInt(parameter.regNumBits.W)
val requestOffset: UInt = UInt(parameter.vrfOffsetBits.W)
val requestMask: UInt = UInt((parameter.datapathWidth / 8).W)
val requestData: UInt = UInt(parameter.datapathWidth.W)
val requestInstruction: UInt = UInt(parameter.instructionIndexBits.W)
}

/** Vector Register File.
Expand Down Expand Up @@ -564,9 +564,9 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
* Probe
*/
@public
val probe = IO(Output(Probe(new VRFProbe(parameter.regNumBits, parameter.vrfOffsetBits, parameter.instructionIndexBits, parameter.datapathWidth))))
val probeWire = Wire(new VRFProbe(parameter.regNumBits, parameter.vrfOffsetBits, parameter.instructionIndexBits, parameter.datapathWidth))
define(probe, ProbeValue(probeWire))
val vrfProbe = IO(Output(Probe(new VRFProbe(parameter))))
val probeWire = Wire(new VRFProbe(parameter))
define(vrfProbe, ProbeValue(probeWire))

probeWire.valid := writePipe.valid
probeWire.requestVd := writePipe.bits.vd
Expand Down