Dev (#15)

* MIP-37: update build.gradle * MIP-37: minor changes
cleverchuk · Aug 26, 2024 · 08e8572 · 08e8572
1 parent 3ad94f7
commit 08e8572
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Showing 2 changed files with 10 additions and 2 deletions.
diff --git a/mips/src/main/java/com/cleverchuk/mips/compiler/lexer/MipsLexer.java b/mips/src/main/java/com/cleverchuk/mips/compiler/lexer/MipsLexer.java
@@ -68,8 +68,8 @@ public MipsLexer() {
     public static final Map<String, TokenType> RESERVED = new HashMap<String, TokenType>() {{
         put("data", TokenType.DATA);
         put("text", TokenType.TEXT);
-        put("ascii", TokenType.ASCII);
         put("asciiz", TokenType.ASCIIZ);
+        put("ascii", TokenType.ASCII);
         put("space", TokenType.SPACE_STORAGE);
         put("byte", TokenType.BYTE_STORAGE);
         put("half", TokenType.HALF_STORAGE);

diff --git a/mips/src/main/java/com/cleverchuk/mips/simulator/fpu/FpuRegisterFileArray.java b/mips/src/main/java/com/cleverchuk/mips/simulator/fpu/FpuRegisterFileArray.java
@@ -32,7 +32,7 @@ public class FpuRegisterFileArray {
     private final Map<String, RegisterFile> registerFile = new HashMap<>();
 
     public FpuRegisterFileArray() {
-        MipsLexer.DECI_TO_FPU_REG.forEach((key, value) -> registerFile.put("$" + value, new DefaultRegisterFile(Integer.parseInt(key))));
+        MipsLexer.DECI_TO_FPU_REG.forEach((key, name) -> registerFile.put("$" + name, createReg(name, Integer.parseInt(key))));
     }
 
     public RegisterFile getFile(String reg) {
@@ -51,6 +51,14 @@ public String regContents() {
         return content.toString();
     }
 
+    private RegisterFile createReg(String name, int id) {
+        if (name.equals("f0")) {
+            return new ReadOnlyRegisterFile(new DefaultRegisterFile(id), 0);
+        }
+
+        return new DefaultRegisterFile(id);
+    }
+
     public static class DefaultRegisterFile implements RegisterFile {
         private final byte[] dflops = new byte[8];