Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

detail work on double to integer conversion #20810

Merged
merged 1 commit into from
Feb 2, 2025
Merged

detail work on double to integer conversion #20810

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
12 changes: 7 additions & 5 deletions compiler/src/dmd/backend/arm/cod4.d
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1284,19 +1284,21 @@ retregs1 = mCX; // hack because no floating support in rest of code
cdb.gen1(INSTR.fcvtzs(0,1,V1 & 31,Rd)); // fcvtzs Rd,V1
break;
case OPd_s64:
cdb.gen1(INSTR.fcvtzs(1,1,V1,V1)); // fcvtzs V1,V1
cdb.gen1(INSTR.fmov_float_gen(1,1,0,7,V1 & 31,Rd)); // fmov Rd,V1
cdb.gen1(INSTR.fcvtzs_asisdmisc(1,V1,V1)); // fcvtzs V1,V1
cdb.gen1(INSTR.fmov_float_gen(1,1,0,6,V1 & 31,Rd)); // fmov Rd,V1
break;
case OPd_u16:
cdb.gen1(INSTR.fcvtzu(0,ftype,V1 & 31,Rd)); // fcvtzu Rd,V1
cdb.gen1(INSTR.sxth_sbfm(0,Rd,Rd)); // and Rd,Rd,#0xFFFF
uint N,immr,imms;
assert(encodeNImmrImms(0xFFFF,N,immr,imms));
cdb.gen1(INSTR.log_imm(0,0,0,immr,imms,Rd,Rd)); // and Rd,Rd,#0xFFFF
break;
case OPd_u32:
cdb.gen1(INSTR.fcvtzu(0,1,V1 & 31,Rd)); // fcvtzu Rd,V1
break;
case OPd_u64:
cdb.gen1(INSTR.fcvtzu(1,1,V1,V1)); // fcvtzu V1,V1
cdb.gen1(INSTR.fmov_float_gen(1,1,0,7,V1 & 31,Rd)); // fmov Rd,V1
cdb.gen1(INSTR.fcvtzu_asisdmisc(1,V1,V1)); // fcvtzu V1,V1
cdb.gen1(INSTR.fmov_float_gen(1,1,0,6,V1 & 31,Rd)); // fmov Rd,V1
break;
default:
assert(0);
Expand Down
18 changes: 14 additions & 4 deletions compiler/src/dmd/backend/arm/disasmarm.d
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1965,7 +1965,12 @@ void disassemble(uint c) @trusted
}
else if (rmode == 3 && (opcode & ~1) == 0)
{
p1 = opcode ? "fcnvtzu" : "fcvtzs";
p1 = opcode ? "fcvtzu" : "fcvtzs";
p2 = regString(sf,Rd);
p3 = fregString(rbuf[4 .. 8],"sd h"[ftype],Rn);
}
else if (sf == 1 && ftype == 1 && rmode == 0 && opcode == 6)
{
p2 = regString(sf,Rd);
p3 = fregString(rbuf[4 .. 8],"sd h"[ftype],Rn);
}
Expand Down Expand Up @@ -2798,26 +2803,31 @@ unittest
unittest
{
int line64 = __LINE__;
string[67] cases64 = // 64 bit code gen
string[73] cases64 = // 64 bit code gen
[
"5E E1 BB FE fcvtzs d30,d31",
"5E A1 BB FF fcvtzs s31,s31",
"1E 78 03 E0 fcvtzs w0,d31",
"7E E1 BB FE fcvtzu d30,d31",
"7E A1 BB FF fcvtzu s31,s31",
"1E 79 03 E0 fcvtzu w0,d31",
"0E 31 BB FF addv b31,v31.8b",
"2E 30 38 00 uaddlv h0,v0.8b",
"0E 20 58 00 cnt v0.8b,v0.8b",
"1E 27 01 00 fmov s0,w8",
"1E 26 00 00 fmov w0,s0",
"1E 78 03 E0 fcvtzs w0,d31",
//"5E A1 BB FF fcvtzs s31,s31",
"1E 23 90 07 fmov s7,#7.000000e+00",
"1E 61 10 03 fmov d3,#3.000000e+00",
"1E 20 43 E0 fmov s0,s31",
"9E 66 03 E0 fmov x0,d31",
"1E 22 C3 FE fcvt d30,s31",
"1E 7F 3B DF fsub d31,d30,d31",

"FD 00 0F E4 str d4,[sp,#0x18]",
"BD 40 43 FF ldr s31,[sp,#0x40]",
"92 40 3C A0 and x0,x5,#0xFFFF",
"92 40 1C C0 and x0,x6,#0xFF",
"12 00 3C 00 and w0,w0,#0xFFFF",
"93 40 7C 60 sxtw x0,w3",
"B9 00 03 A1 str w1,[x29]",
"1A 9F A7 E0 cset w0,lt",
Expand Down
Loading