MdePkg/BaseLib: RISC-V: Add function to update stimecmp register

stimecmp is a CSR supported only when Sstc extension is supported by the platform. This register can be used to set the timer interrupt directly in S-mode instead of going via SBI call. Add a function to update this register. Cc: Michael D Kinney <[email protected]> Cc: Liming Gao <[email protected]> Cc: Zhiguang Liu <[email protected]> Cc: Andrei Warkentin <[email protected]> Signed-off-by: Sunil V L <[email protected]> Reviewed-by: Andrei Warkentin <[email protected]>
ellyq · Jan 11, 2024 · 8ae17a7 · 8ae17a7
1 parent fd629ef
commit 8ae17a7
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diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
@@ -191,6 +191,11 @@ RiscVReadTimer (
   VOID
   );
 
+VOID
+RiscVSetSupervisorTimeCompareRegister (
+  IN UINT64
+  );
+
 VOID
 RiscVEnableTimerInterrupt (
   VOID

diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
@@ -96,6 +96,9 @@
 /* Supervisor Protection and Translation */
 #define CSR_SATP  0x180
 
+/* Sstc extension */
+#define CSR_STIMECMP  0x14D
+
 /* Trap/Exception Causes */
 #define CAUSE_MISALIGNED_FETCH          0x0
 #define CAUSE_FETCH_ACCESS              0x1

diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
@@ -21,3 +21,10 @@
 ASM_FUNC (RiscVReadTimer)
     csrr a0, CSR_TIME
     ret
+
+//
+// Set Supervisor Time Compare Register
+//
+ASM_FUNC (RiscVSetSupervisorTimeCompareRegister)
+    csrw  CSR_STIMECMP, a0
+    ret
-Original file line number
+Diff line change
@@ Expand Up / @@ -191,6 +191,11 @@ RiscVReadTimer ( @@
       VOID
       );
+    VOID
+    RiscVSetSupervisorTimeCompareRegister (
+      IN UINT64
+      );
     VOID
     RiscVEnableTimerInterrupt (
       VOID
@@ Expand Down @@