Add Mixed HDL Blink example

[umarcor]

Close #334

NOTE: this PR is based on #334. However, in #334 container images are used to workaround GHDL being missing in Fomu toolchain. Here, open-tool-forge/fpga-toolchain is used instead. Using fpga-toolchain or containers for VHDL and/or mixed HDL projects is equivalent. Moreover, fpga-toolchain seems to be a valid replacement for part of Fomu toolchain (im-tomu/fomu-toolchain#20). Therefore, I will keep this PR as a draft until either #334 or im-tomu/fomu-toolchain#20 are merged. When those are merged, I will update the docs and Makefiles accordingly.

This PR adds subdir mixed-hdl/blink. It is equivalent to verilog/blink or vhdl/blink, but instead of using a single HDL language, VHDL and Verilog are used at the same time. Four possible use cases are provided:

• blink.vhd + clkgen.v
• blink.v + clkgen.vhdl
• blink.vhd + clkgen.vhdl
• blink.v + clkgen.v

The makefile builds the first one by default, but users can change between them by modifying two envvars in the Makefile: VHDL_SYN_FILES and VERILOG_SYN_FILES.

The README and the docs are updated.

NOTE: instantiating Verilog modules/components with parameters/generics into VHDL works ok, but there seems to be some issue when VHDL components with generics are instantiated in Verilog. See ghdl/ghdl-yosys-plugin#136. Nevertheless, the Verilog modules instantiated in this PR do not have parameters/generics; thus, that's not a blocking factor.

[mithro]

@xobs - Do we know any VHDL supporters who could review this?

[mithro]

FYI - @tcal-x

[umarcor]

@mithro, I will update #334 and this for using the "new" toolchain. Then, I'll ping some reviewers.

[umarcor]

/cc @GlenNicholls @hackfin @ktbarrett @LarsAsplund @marph91 @Paebbels @rodrigomelo9 @tgingold @tmeissner

Guys, would you please have a look at this PR? It's about mixed HDL synthesis (with ghdl-yosys-plugin and Yosys).

• There is an existing Verilog example: https://github.com/umarcor/fomu-workshop/tree/mixed-hdl/verilog/blink
• In Add VHDL Blink example #334, I rewrote the example in VHDL (single file, apart from vendor components): https://github.com/umarcor/fomu-workshop/tree/mixed-hdl/vhdl/blink
• In this PR, Verilog and VHDL are mixed: https://github.com/umarcor/fomu-workshop/tree/mixed-hdl/mixed-hdl/blink

All examples describe the same circuit/design. The purpose is for users to see the differences/equivalencies between languages, and most important, to know how to combine them.

Corresponding docs are found at https://umarcor.github.io/fomu-workshop/hdl.html

[tmeissner]

/cc @GlenNicholls @hackfin @ktbarrett @LarsAsplund @marph91 @Paebbels @rodrigomelo9 @tgingold @tmeissner

Guys, would you please have a look at this PR? It's about mixed HDL synthesis (with ghdl-yosys-plugin and Yosys).

I will have a look 🙂

[tmeissner]

The PR looks good for me as an VHDL (and part time Verilog) guy. The code looks similar to that we have at work when mixing VHDL & Verilog code to process it with the vendor tools (Synplify, Lattice LSE and Vivado in our case).

[mithro]

@umarcor - I'm happy to move forward, are you ready for this to be merged?

[umarcor]

@mithro sure! Let's have it merged, and we will then think about how to rework the general HDL related explanations. As you have seen, @juanmard is putting this workflow under heavy testing, and many lessons are being learnt to be then applied here.

[mithro]

Sounds good to me!