High level design plans

Performance

• C generation almost acceptable (faster vtable init left)
• Python is slow. pypy plus static typing annotations, or reimplement parts in rust?
• Develop DML code generator practices for avoiding huge banks
  • Dynamic register_view
• Offer hands-on help to SSM and PSG infra
  • proactively?

Coroutines

• hooks/channels

Conditional imports

• may come with a larger loosening of order dependency rules for early evaluated expressions, i.e., early cross-obj param refs are ok if param dependency graph doesn't have cycles

Dynamic objects

Two options:

1. Truly dynamic objects, e.g. instantiation-time config of array sizes
2. Optionally hidden elements, e.g. disabled registers

• dynamic ports are problematic, port arrays can't be port objects
• registers: compile-time overlap checks not possible, must allow mutually exclusive regs with overlap. Also need dynamic offsets (even sizes?).
• dynamic register_view
  • two kinds of disabled registers: flexible instantiation-time config (overlapping, dynamic offset) visible in register_view; run-time toggle is a different use case, should not show up in register_view.

RAII

Avoid the need for explicit allocation by supporting automatic destruction when variables go out of scope. Exact

• primitive types (strings and data blobs)
  • Includes RAII semantics for expressions like "x" + "y".
  • Unclear relation between RAII string type and const char * in type system; likely need implicit conversions.
• vectors